Synthesis fails for axi_register_slice

Question

My synthesis runs have been working fine until a recent set of innocuous modifications to the source. All of a sudden I'm getting errors in synthesis that have to do with an axi_register_slice I have in my cl_top.sv. I've triple checked the source is there and deleted the encrypted output. Has anyone else run into this problem? Does anyone have any ideas I can try? I'm unfortunately not able to share my source.  
  
The errors happen in RTL Elaboration and look like the following:  
  
INFO: \[Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189]  
        Parameter C_FAMILY bound to: virtexuplus - type: string   
        Parameter C_DATA_WIDTH bound to: 109 - type: integer   
        Parameter C_REG_CONFIG bound to: 1 - type: integer   
ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189]  
ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:2300]  
ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v:58]  
ERROR: \[Synth 8-5809] Error generated from encrypted envelope. \[/home/centos/cl_base/build/src_post_encryption/cl_top.sv:17]

Thanks in advance,  
  
-Jack

Answer

Hello JWadden,  
Could you please let us know which HDK version you are using ?  
  
You mentioned "recent set of innocuous modifications to the source", is it possible that after reverting these changes you are able to synthesize successfully ?  
  
--Thanks  
Siddharth

Answer

This was resolved. Thanks for the response!

Answer

I just updated to HDK 1.4.7 and got the same synthesis errors. It attempted to install patch AR71715. Vivado's output looks like the following:

```
INFO: Setting up environment variables
INFO: Base vivado version is Vivado v2018.2_AR71275_op (64-bit) ; Checking if patch AR71715 needs to be installed
INFO:  SDX patch AR71715 is valid for Vivado v2018.2_AR71275_op (64-bit)
INFO: Using Vivado v2018.2_AR71275_op (64-bit)
VIVADO_TOOL_VERSION is v2018.2
INFO: Using HDK shell version shell_v04261818
INFO: HDK shell is up-to-date
INFO: HDK shell is up-to-date
INFO: HDK shell is up-to-date
INFO: DDR4 model files in /home/centos/r/aws-fpga/hdk/common/verif/models/ddr4_model/ were built with Vivado v2018.2_AR71275_op (64-bit)
INFO: CL_DIR is /home/centos/r/cl_basedir
INFO: AWS HDK setup PASSED.
 ```

I just clarified with a collaborator that we actually did not change the source before synthesis stopped working. Any thoughts?  
  
-Jack

Answer

Hey,  
We have run synthesis on cl_dram_dma example and do not see any issue with axi_register_slice_v2_1_15_axic_register_slice.  
  
Is is possible to share your synthesis log file with us ? We will have a look at it.  
  
-Thanks  
awsSiddharth

Synthesis fails for axi_register_slice

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