Clock frequency of CL is fixed or it can be changed for target design?

Question

Hi,  
  
I am using AWS F1 for FPGA development from an year  I had this basic question  from long time. Right now I have selcted a0 clock recipe for my design which is main clock. As per my understanding clock frequency should depend on critical path in design and  may change from design to design or is it like in AWS environment if it will see that for given clock recipe if it finds critical path then it will throw an error in synthesis?   
We can choose any clock frequency a0 or a1 for CL design ?  
  
Another question I had , I am running all my design in non gui mode and have extended from hello world design. After running simulation or synthesis if I want to open project in gui mode what are the steps to do it ? Is there any documentation available for the same ?

AWS-zhcz · Answer

Hi aiquanta,  
  
Understood. It's feasible to create a local simulation project. That would require to manually add in all the per-compiled libraries and testbnech components to run RTL level simulation in project mode in GUI. Unfortunately, our whole verification environment is set up in the batch mode only in order to provide better compatibility with 3rd party simulators. We don't have a support for Vivado simulation running in project mode that you can directly leverage.  I'll take the feedback to the development team to see if this is something we could support going forward.  
  
Thanks,  
  
- Chen

aiquanta · Answer

Hi Chen ,  
  
Thanks for the clarification. Sorry for the confusion. From GUI I meant VIVADO gui.

aiquanta · Answer

Hi Chen,  
  
I can open VIVADO gui from command but my query is as following.  
  
Till now I have always running in non project mode. I just use provided scripts (makefile and all) to run simulation. My query is if I can run same project from VIVADO GUI so that once it completes I can see source file edit it there and run it again.  
  
Right now I run everything in non project mode and then once test case finishes I just open waveform in vivado. To open a project into vivado I need project file. But I am not sure if any project file is created when I run in non project mode. If no project file is created in that case how I can run simulation in project mode?

AWS-zhcz · Answer

Hi aiquanta,  
  
You should be able to run Vivado GUI using command `vivado` once DCV is up and running. Please let me know if you see any problem.  
  
Thanks,  
  
- Chen

AWS-zhcz · Answer

Hi aiquanta,  
  
Thank you for using AWS F1 instance. Regarding to the question on clock frequency, you're correct. Critical path will be different from design to design, or sometimes even from one build to the other. AWS provide several clocks that we think might be good fits for customer designs with different needs. Customer is required to choose from the clock group recipes (https://github.com/aws/aws-fpga/blob/master/hdk/docs/clock_recipes.csv) and cannot use arbitrary clock frequency. In addition, we have a dynamic clock configuration feature (https://github.com/aws/aws-fpga/blob/master/hdk/docs/dynamic_clock_config.md) in case you want an option to slow down design's clock frequency to meet timing.  
  
For the GUI mode, we do have a NICE DCV support (https://github.com/aws/aws-fpga/blob/master/developer_resources/DCV.md). Please follow this page to set up the environment. Hope this helps!  
  
Thanks,  
  
- Chen

Clock frequency of CL is fixed or it can be changed for target design?

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