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cl_dram_dma/build/constraints/cl_pnr_user.xdc contraints good for any cl?

0

Looks like in the dram_dma exmple there are a number of floor planning directives to improve timing/routability.
I currently do not use DRAM or the DMA in my cl, should I include these constraints in my cl since these interfaces cannot be eliminated from the shell 9but only tied off)? is there more documentation on what these constraints are doing and how they were derived?

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Calcul
Balises
Développement FPGA
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English
metaflows
demandé il y a 4 ans166 vues
1 réponse
0

Hi,

Yes you may use the floorplan constraints in CL_DRAM_DMA example as a reference for your CL. Note that the cells referenced in the constraints file are specific to CL_DRAM_DMA design, so you need to review these for your design. However, the pblock sizes defined here should work for any CL.

Please contact us if you need any additional details.

Thanks!
Chakra

AWS
awschakra
répondu il y a 4 ans

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