DMA registers

Hello,

The DMA registers are accessible on PF0 BAR2 and we use the Xilinx XDMA IP, so you can refer to the XDMA IP Product Guide for details: https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf#page=42

The Bar mapping is listed here: https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Fpga_Pcie_Memory_Map.md#memory-map-per-slot

Let us know if you need any further information and we'd be happy to help.

-Deep

Thanks

the sh_ddr.sv does not have any interface to program the registers in DDR controllers.
I believe there should be one.
Is this done with the same interface as for data read/write?

Hi,

All the DDR Controllers are managed entirely by the Shell. Customers are required to connect the "stats" interface exposed by sh_ddr.sv to the corresponding interface from the Shell in cl_ports.vh.

https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#ddr4-axi states:
WARNING: If the stats interfaces are not connected, the DDR controllers will not function. However, the CL developer should not otherwise use them since they are specific to Shell management functions. If the DDR controllers are not used by the CL, then the interfaces should be left unconnected.

An example of such connection is shown below:
https://github.com/aws/aws-fpga/blob/master/hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv#L643-L665

Hope this helps. Please reach us if you have any questions.

Thanks!
Chakra