Data transfer using f1.x4large

Hi,
I am new to AWS FPGA Development.
My task is, Using f1.x4large instance, I need to transfer packetized data from one FPGA to another FPGA.
After power-on, by design one FPGA is defined as Sender and the other as Receiver.
And Sender starts sending packets one at a time and the gap between the two packets is huge.
On receiving the correct packet, the receiver acknowledges this with an ACK packet.
Both Sender and Receivers maintain transmit and receive packet counters.
This data transfer happens without driver involvement.
The driver should be able to access the transmit and receive count register and other registers.

I have gone through the example DMA test cases.
I couldn't understand how to communicate without any driver involvement.

Appreciate your help.

Regards,
Venkat