DDR write access problem

Hello,

I am implementing an FPGA IP connected to the AWS shell through AXI interface. The IP performs : loading data from DDRA, calculation on these data storing the result in DDRB The IP integrates the following AXI interfaces : - S00 : Full AXI , Write access to DDRA to transfer data from host application - M00 : Full AXI , Read access to DDRA for loading data to be computed - S01 : Lite AXI for configuration and debug - M02 : Full AXI , Write access to DDRB for storing partial results - S02 : Full AXI , Read access to DDRB to transfer data to host application

The computing part initiates accesses to DDR : 2 x 2 beats of 512 data bit, for a basic version

The FPGA design is based on the IPI CDMA Test Example. Test are performed with C file provided with the HDK on F1 instance

Data are transfered from host to DDRA correctly. I have implemented registers in the kernel to check the reading access from DDRA The problem is on reading results from DDRB. DDRB data are set to 0. I checked that data are correctly read by replacing DDRB data by constant data. -> OK

I have to run simulation to check axi_awvalid, axi_awready, axi_wvalid, axi_wready and axi_wlast . But when I try it I get the following error message : "ERROR: [VRFC 10-449] cannot open file "/opt/Xilinx/Vivado/2021.2/data/xsim/ip/blk_mem_gen_v8_4_5/blk_mem_gen_v8_4_5_synth_comp.vdb" for writing"

Can you tell me how to fix this issue?

Best Regards