--interactive impl fails

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Hello,
I see there is a new feature in xocc to synthesize and implement and RTL kernel in Vivado and feed the result back into to the xocc flow (at least, that is how I understand it).

When I try to do this in the F1 development AMI I get an error that the kernel.xml file is not present. It looks like there is a directory tree in _x/link/int that is not yet populated by the makefiles in the rtl_vadd example.

Is this flow expected to work?

Thanks!

simonSN
posta 5 anni fa172 visualizzazioni
7 Risposte
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Hi simonSN, the --interactive switch is a method of opening the Vivado project as part of an XOCC compile. One of the requirements is that a previous run exists before using this switch. If you run XOCC without this switch to completion, and then without cleaning the project run it again with the switch, it should open the Vivado project.

con risposta 5 anni fa
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Got it, great, I'll give that a try.

Once in Vivado do I need to take the design through just synthesis, both synthesis and implementation, or can I choose how far to go?

Thanks!

simonSN
con risposta 5 anni fa
0

You can choose how far to go. Depending on the changes you make, you can either re-save the .dcp file in the state it was in (synth or impl), or re-run Synthesis or Implementation to get a new DCP checkpoint. If you want to then use the modified DCP you can use --reuse_impl <dcp_file> or --reuse_synth <dcp_file> depending on the state it was saved in.

con risposta 5 anni fa
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As far as I can tell this flow doesn't seem to allow me to re-synthesize my own IP (the RTL kernel).

Is there a way to do that so I can change the synthesis options?

Thanks

simonSN
con risposta 5 anni fa
0

With the --interactive switch, at the earliest you are already examining a Synthesized netlist. You are able to edit the netlist and re-save the .dcp, but you can only move forward in the flow to implementing the design. If you are trying to add Synthesis options, this should be done before getting to this stage. You may want to look at the Out of Context Synthesis section of the RTL Kernels documentation if you are looking to do this with your RTL kernel. https://www.xilinx.com/html_docs/xilinx2018_3/sdaccel_doc/creating-rtl-kernels-qnk1504034323350.html

con risposta 5 anni fa
0

Ok, thanks that helps.

simonSN
con risposta 5 anni fa
0

Just to note on my previous reply, as the current AMI supports 2018.2, you can refer to the 2018.2 version of the documentation for RTL Kernels: https://www.xilinx.com/html_docs/xilinx2018_2/sdaccel_doc/creating-rtl-kernels-qnk1504034323350.html however this feature is still the same in 2018.2.

con risposta 5 anni fa

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