How to add a wire to connect an HLS kernel and an RTL Kernel in Vitis

Hello,

Xilinx strongly recommends the usage of AXI-Stream connections between two kernels, as it is a much safer mechanism and allows more automation by the tools.

It is however possible to use the Vitis "connect" connectivity option to directly and manually connect individual kernel ports. When using this feature, Vitis will not perform any checks. The user is therefore responsible to ensuring the correctness of the specified "connect" option. This is considered an expert feature. You can find more details about this feature in the online documentation:
https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/vitiscommandcompiler.html#clt1568640709907__section_gzy_xkc_w4b