Stuck at Hello World synthesis stage

Question

Hi. I am using FPGA Developer AMI 1.11.0 and was running hello_world example from https://github.com/aws/aws-fpga/blob/master/Vitis/README.md, using "make all TARGET=hw DEVICE=$AWS_PLATFORM"  
I am using m5.xlarge on us-west-1.  
  
Unlike the run using previous AMI version, it no longer progresses after the point:  
==============================  
\[11:44:52] Run vpl: Step create_project: Completed  
\[11:44:52] Run vpl: Step create_bd: Started  
\[11:45:23] Run vpl: Step create_bd: Completed  
\[11:45:23] Run vpl: Step update_bd: Started  
\[11:45:23] Run vpl: Step update_bd: Completed  
\[11:45:23] Run vpl: Step generate_target: Started  
\[11:46:36] Run vpl: Step generate_target: Completed  
\[11:46:36] Run vpl: Step config_hw_runs: Started  
\[11:46:41] Run vpl: Step config_hw_runs: Completed  
\[11:46:41] Run vpl: Step synth: Started  
==============================  
When I type "top" - vivado CPU utilization goes down to near 1%. (not killed - just not working)  
  
So I looked at "./_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/vivado.log", and it has ended at the point  
==============================  
\[Mon Sep  6 11:46:44 2021] Launched my_rm_synth_1...  
Run output will be captured here: /home/ec2-user/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/hello_world/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/my_rm_synth_1/runme.log  
\[Mon Sep  6 11:46:44 2021] Waiting for my_rm_synth_1 to finish...  
==============================  
  
From comparing with logs with previous version, I think Vivado should get launched at this point to do synthesis, but it is not happening.  
  
I know it is a vague description of the problem, but is there some commands I can try to figure why it has stopped working? I suppose Vivado program is waiting for some routines to finish, and they are not responding back - but not sure what to check.  
  
Thanks.

Answer

--- deleted ---

Answer

Thanks. I found out the reason. It turns out when I use the FPGA Developer AMI (Linux 2) - the RHEL version, the above described problem happens. When I switched back to the centos version, it runs as it should.  
I suppose that RHEL version requires more memory - The Xilinx recommend instance type is m5.2xlarge - I was intentionally using m5.xlarge to reduce the cost.

Answer

Hello,  
  
Can you also look at the memory being consumed? Since it is a larger device, usually if memory becomes an issue, it'll start using the swap which is significantly slower and could cause such an issue.  
  
Let us know if the memory usage looks ok, and we can look into it further.  
  
Thanks,  
  
Deep

Answer

-- duplicated post -- self-deleted

Answer

Hi,  
  
I believe this was due to a bug and a discrepancy in the AL2 AMI as compared to the Centos AMI. AL2 AMI has the XILINX_HLS environment var set in the PATH and a bug in the hdk_setup script added those paths to the PYTHONPATH variable. This should be fixed in the latest commits released in the developer kit and you should be able to use the AL2 AMI without seeing this issue.  
  
To get the latest commits, either clone the Developer Kit again or simply do a git pull on your clone.  
  
Hope this helps!  
  
-Deep

Stuck at Hello World synthesis stage

Unlike the run using previous AMI version, it no longer progresses after the point:

So I looked at "./_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/vivado.log", and it has ended at the point

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