AXI master address width

Question

Hello,  
I seem to have a design that is barely routable. I found that if I reduce the AXI master address width to 16 bits it routes (but does not function). At 64 bits it does not route.   
  
I only need to transfer 528 bytes of data to/from the kernel.  
  
Is it possible to restrict memory to a much smaller address space? I know the documentation says 64 bits is required but want to see if there are any workarounds.   
  
I don't think using scalars would work because they cannot be read back.   
  
Thanks!

Answer

Hello,  
  
I don't know if changing the width will work as that seems to be set. However, routability issues are usually caused by a design that has a very high percentage of device resource utilization. Can you share what the resource utilization is for your design? If below say 70% then I think we would need to look at your design in order to see what is causing the routability issues. If that is the case, then can you also share your design? If above that, then the next step would be to reduce your design logic in order to see if the design can then be routed.   
  
Thank you,  
Scott

AXI master address width

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