Run post-processing host code in parallel with F1 kernel

Question

Hi  
I have an application that needs some serious post-processing of the data output from a kernel running on the F1.   
By breaking the data that needs to be processed into blocks, I want to run the post-processing host code in parallel with the kernel. (ie while kernel is working on block k, the host post-processing code is working on block k-1).  
I have tried to implement this following the overlap_c example, however, from inserting timers in the code I only see serial operation of the post-processing code (although the IO overlaps with the kernel execution).  
Can anyone point me to an example, as this must be a common problem?  
  
Also, I can write the post-processing code as a (software) OpenCL kernel. Could I run hardware kernel(on the F1) and software kernel(on the vCPUs) , in Vitis, with the kernels communicating over streams?

Accepted Answer

Hello,  
  
The overlap_c example shows how to overlap multiple requests from the host to the FPGA. This is expained in the header of the source code:  
https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/host/overlap/src/host.cpp#L39  
  
If you are looking to overlap computation on the host and computation on the FPGa, a better example to look at would be this Lab:  
https://github.com/Xilinx/SDAccel-AWS-F1-Developer-Labs/blob/master/modules/module_02/README.md  
Part 2, Step 4 is where you will see a specific example of this. But I recommend that you start reading from the beginning of the lab.

Run post-processing host code in parallel with F1 kernel

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