Hey guys,
I was wondering about the provenance of these three constraints that appear in some but not all of the example designs. Under what circumstances are they required? In my designs, now based off cl_dram_dma, (which has them commented out)https://github.com/aws/aws-fpga/blob/v1.4.20/hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc#L64), only the latter two correctly resolve.
set_clock_groups -name TIG_SRAI_1 -asynchronous -group \[get_clocks -of_objects \[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group \[get_clocks -of_objects \[get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
set_clock_groups -name TIG_SRAI_2 -asynchronous -group \[get_clocks -of_objects \[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group \[get_clocks drck]
set_clock_groups -name TIG_SRAI_3 -asynchronous -group \[get_clocks -of_objects \[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group \[get_clocks -of_objects \[get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
Can i safely remove all three?