Can't forward placements constraints to F1 FPGA

Question

Hi,

Working in Xilinx Vitis flow for F1 FPGA instance
I am trying to forward placement constriants on F1 FPGA in the synthesis/placement stage but the vivado said there is collision with current constraints probably becuase the vitis flow with AWS shell provide constrints on the user logic locations

So I tried to put placement constraints on the use logic side but again got error from impl process and terminated the execution of the synthesis.

Please advise how to forward placement constraints to my user logic in a way that I can put my logic in the place that was dedicated for the user

Thanks

Answer

Dear customer

Thank you for your interest in using AWS. Vitis flow does provide option to add placement constraints. The document below can provide details on how to enable placement constraints in vitis

https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/vivado-Options

If you are looking for injecting SLR constraints to vitis, it can also be done via config files. 
In your script or makefile, you need to have something similar to this :
v++ -t hw --platform […] --config ./vmult_vadd_SLR0.cfg […]
 
for example using a modified version of the github example Vitis_Accel_Examples/sys_opt/slr_assign, in the file vmult_vadd_SLR0.cfg, assuming the kernels are named vmult_1 and vadd_1, we’d get :
[connectivity]
slr=vmult_1:SLR0
slr=vadd_1:SLR0

Also can you please provide the log and/or exact conflict errors you are seeing for further help with the issue if the provided information did not resolve your issue.

Thanks

Can't forward placements constraints to F1 FPGA

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