Simulation - File Dump to a memory

Hello Gogul,

To achieve this, you need to write a script or code in your testbench to read the text file, parse the data, and then use the tb.poke function to load the memory connected to the SHELL's PCIS/DMA.

Could you please follow the below Steps to Load Data from Text File to Memory Read Data from the Text File:

Open and read the text file line by line. Parse each line to get the 32-bit data. Write Data to Memory:

Use the tb.poke command to write the data to the specified address.

Detailed Steps

1. Reading the Text File Assuming you're using a scripting language like Python for this purpose, here’s an example of how to read the file and parse the data:

# Python script to read the text file and prepare data for memory loading

def read_data_from_file(file_path):
    data_list = []
    with open(file_path, 'r') as file:
        for line in file:
            # Convert the line to 32-bit integer (assuming data is in hexadecimal format)
            data = int(line.strip(), 16)
            data_list.append(data)
    return data_list

2. Writing Data to Memory Using tb.poke The tb.poke command needs to be executed in your simulation environment. Below is a general approach assuming you’re using a SystemVerilog or similar environment.

This is just a general approach, you will need to adjust it to suit what you want to use it for

Example SystemVerilog Code:

module testbench;

    // Parameters
    parameter ADDR = 32'h00000000;  // Starting address
    parameter AXI_ID = 4'b0001;     // AXI ID (example)
    parameter DataSize = 32;        // Data size
    parameter PORT_DMA_PCIS = 0;    // Interface (example)

    // Function to poke data into the memory
    task load_memory(input [31:0] address, input [31:0] data);
        tb.poke(.addr(address), .data(data), .id(AXI_ID), .size(DataSize::UINT32), .intf(PORT_DMA_PCIS));
    endtask

    initial begin
        // Read data from file
        int file_handle;
        int line;
        reg [31:0] data;
        integer i;

        file_handle = $fopen("data.txt", "r");  // Open the text file
        if (file_handle == 0) begin
            $display("Error opening file.");
            $finish;
        end

        // Load data into memory
        i = 0;
        while (!$feof(file_handle)) begin
            line = $fscanf(file_handle, "%h\n", data); // Read 32-bit data from file
            if (line != 0) begin
                load_memory(ADDR + i*4, data);  // Assuming 4-byte increments
                i = i + 1;
            end
        end

        $fclose(file_handle);  // Close the file
    end

endmodule

Summary of it Read Data from File:

The Python script reads hexadecimal values from the text file and converts them to 32-bit integers. Load Data into Memory:

The SystemVerilog code opens the file, reads 32-bit data values, and uses the tb.poke command to write the data into memory at the specified address.

Adjust the ADDR parameter to set the correct starting address, and the DataSize parameter to match the data size being used.

Commands Overview :- Python Script: Reads data from the text file and stores it in a list.

SystemVerilog Code: Opens the text file, reads each line, and writes data into memory using the tb.poke command. This approach ensures that your testbench loads the memory with the specified 32-bit data from the text file accurately. Adjust paths, addresses, and parameters according to your specific testbench setup and requirements.

Hi @Adeleke Adebowale J

The first data to the location 0 is written properly as shown below.

But the second data is again loaded to the first location instead of the second location. Address has to be incremented by 4. And 'wea[3:0]' is enabled before 'ena' is enabled and address is 0 there so the second data is written to the first location.