How to solve the situation that the compilation process of fpga program is terminated without error？

Hello, I am currently using Vitis hls2021.2 to compile an FPGA program. The instance I use is t2.2x. My problem is that there is no error during the compilation process, But my compilation log shows that the compilation is terminated when the fifth task is performed. And before the termination, the log has no output for nearly two hours

[05:01:29] Phase 1 Physical Synthesis Initialization
[05:03:00] Phase 4.1.1.2 BUFG Replication
[05:03:00] Phase 4.1.1.3 Post Placement Timing Optimization
[05:08:04] Phase 4.1.1.4 Replication
[05:11:06] Phase 4.2 Post Placement Cleanup
[05:11:06] Phase 4.3 Placer Reporting
[05:11:06] Phase 4.3.1 Print Estimated Congestion
[05:11:37] Phase 4.4 Final Placement Cleanup
[05:24:17] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 01h 13m 56s 

[05:24:17] Starting logic routing..
[05:26:19] Phase 1 Build RT Design
[05:29:51] Phase 2 Router Initialization
[05:29:51] Phase 2.1 Fix Topology Constraints
[05:29:51] Phase 2.2 Pre Route Cleanup
[05:30:22] Phase 2.3 Global Clock Net Routing
[05:43:32] Phase 2.4 Update Timing
[05:47:05] Phase 2.5 Update Timing for Bus Skew
[05:47:05] Phase 2.5.1 Update Timing
[05:48:36] Phase 3 Initial Routing
[05:48:36] Phase 3.1 Global Routing
[05:52:09] Phase 3.2 Update Timing
[05:57:44] Phase 4 Rip-up And Reroute
[05:57:44] Phase 4.1 Global Iteration 0

I don't understand if this is caused by me not selecting the f1 instance? Because my personal understanding is that the generation of the xclbin file has nothing to do with having fpga or not. I'd like some help with generating the error, I'll add later if detailed code is needed