How to implement a design which spans across two FPGAs?

Dear customer

Thank you for reaching out to aws. In this case, you need to partition the design into the CL region of two FPGAs, very similar to what you would have done in a non-F1 case, the difference being with F1, the shell part of the design that involves PCIe interface, basic DDR-C etc are by default generated for you as part of the shell. The P2P communication between the two FPGAs is through PCIe. Please refer to https://github.com/awslabs/aws-fpga-app-notes/tree/master/Using-PCIe-Peer2Peer for further guidance on using PCIe P2P.

Thanks

Hi Kishoreataws,

Thanks for the response.
As you mentioned the communication needs to happen through PCIe, does that mean there is not Wire connection between the two FPGAs?
In other words, is it possible a continuous stream of data (signals) between the FPGAs?

Regards,
Venkat

Dear customer

Thanks for the follow up. Thats correct, PCIe path is the only link available for communication between the FPGAs. There is no direct pin connections between the FPGAs

Thanks

thanks for the response.

Hi Kishore,

I looked at the APP Note -Using-PCIe-Peer2Peer and understand how to communicate between two FPGAs.

Is there a verilog/system verilog testbench env with a testcase or so, so that I can try this before building FPGA image.?
Please point to any customer provided/created or AWS created testbench env, if any available.

I guess this would help for me to make sure my client logic also of error free.

Appreciate your help.

Regards,
Venkat

Dear customer
Thank you for the follow up. For the peer 2 peer communication between the FPGAs use case you are interested, what is the data rates that you are targeting?
Regarding the test bench, the addresses can just be mapped to host memory and see if that works and other FPGA access should also work because all it is doing is accessing some external address. Peer-to-Peer transfer is essentially accessing destination FPGA's PF0-BAR4 address space. Therefore you'll need a test to verify if CL in source FPGA is capable of generating those addresses. For simulations, you may define an address space in host memory and verify if CL can access that space. The Shell BFM provided in aws-fpga TB supports this. Please feel free to contact aws if you have any follow up questions.

Thanks