Read and write buffer of unequal size does not work in Vitis

Hi Shashwat, would it be possible to get the kernel code or Vitis design so we can do some profiling and take a closer look at the data transfers?

Also in the host code, you seem to note the data variables on lines 70-71, but they are the same number. I assume that these values are changed appropriately for the unequal size run?

const cl_uint number_of_words = 2048; // 16KB of INPUT data
const cl_uint number_of_words_out = 2048;//8KB OUTPUT

Hello!
Thank you so much for your reply.
Please use this link to download Vitis project files https://drive.google.com/drive/folders/1JAClKAOgykuf0L19LjX5vVGSiMy23TQz?usp=sharing . I have added hierarchy diagram for clarity.

Info about kernel: I Followed the mentioned link's example https://github.com/Xilinx/Vitis-Tutorials/tree/master/docs/getting-started-rtl-kernels/reference-files/src/IP to integrate my design. As given in the example, I am using 2 masters and one slave. For my design, I am using one master to read the value and other to write the value in memory. In the place of Vadd_A_B_example_adder.v (compute unit of example), I added an AXI Stream logic to integrate my hardware design. My hardware design adds 15 to every alternate value it receives and outputs only these values which are incremented by 15. Hence I generate 8KB of output from 16KB input.

Sorry for the confusion, I have used ulong and uint in clCreateBuffer in line 247 and 254. But now I have added a clear host code in the project folder.

Thanking you,
Shashwat

Edited by: shashwats on Jun 22, 2020 12:00 PM

Hi Shashwat, I started with using the RTL Kernel reference instructions as you mentioned to recreate the Vitis project followed with replacing the sources with the files you provided. In testing this and trying to compare the equal vs. unequal sizes, I am seeing that the behavior is the same even when changing the values for the constant. Maybe I am misinterpreting the design, could you let me know what values are intended to be changed to show the issue?

Hello!
Code mkAWS_32io_h.v is specifically designed to output only alternate input values added with 15. It will not have equal size of input and output buffer. Therefore in Top_wrapper.v, line 74 and 75 have these values.

localparam integer  LP_DEFAULT_LENGTH_IN_BYTES = 16384; //INPUT BYTES
localparam integer  LP_DEFAULT_LENGTH_IN_BYTES_out = 8192; //OUTPUT BYTES

I have added the code mkAWS_32io.v which adds 15 to all the input values in the google drive link. This will have equal input and output buffer.

Thanking you,
Shashwat

Hi Morris,

I have realized that the problem is not due to unequal buffer size rather it is because the output from kernel does not come every clock cycle i.e. stalls are there in the design (output comes every alternate clock cycle). But I am not able to understand how does the irregular flow of output is stopping writes into the memory.

I tried to tap the AXI4 LITE signals during hardware emulation using live waveform viewer. Vivado opened up but no green or red lines of signals were present in the simulation window. Is there a way to fix this?

Is there any other debug technique that can be used to debug RTL kernel in hardware emulation?

Thanking you,
Shashwat

Hello!

There was some other issue. Read and write buffer of different sizes work absolutely fine.

Solution: There is no global reset signal to the kernel therefore the verilog design needs to be reset before running. So that registers have some known initialise value rather than some garbage values.

Thanks,
Shashwat