Replicating SDAccel's clock scaling in HDK flow

Hi,

I find the automatic clock scaling at the end of the SDAccel flow very handy as it allows one to still run designs that miss the timing target without recompiling them with a different clock or clock recipe.

Is there a way to enable a similar mechanism in HDK? If not, what would be the simplest way to replicate it?

It doesn't necessarily have to be automatic, it would be perfectly fine to manually tune the clock frequency at runtime for example through OCL.

The best I can think of is to use a Clocking Wizard and expose its AXI-Lite interface through OCL and add CDC logic on every interface of my CL module (e.g., AXI Clock Converters). Would this make sense? Would you see any simpler alternative?

Thanks,

Mikhail