Combinatorial Loop

Question

Hello,  
  
I am using Vitis flow to create an RTL kernel.  
  
I have an intentional 'combinatorial loop':  
In the design, multiplexers are used to connect some number of LUTS in different ways based on a register value.   
Register value will never be such, that LUTS are connected in an actual loop, but the synthesis tool still sees it as one.  
  
Is there a way to write a constraint to break the loop during Timing analysis, like when working with the Vivado on a local board.  
  
If there is none, and loops are generally prohibited, do you know if it is noted in any documentation, so I can deliver that as a formal confirmation?   
  
Thanks in advance,  
Djordje

Answer

Thank you both for clarification,  
  
I know that the synthesis tool can't know the states of register, and that the register can access unwanted state in many ways.  
I just wanted to confirm, and get somewhat of a more 'formal' way, to notify lead designer that it's not supported.  
The ERRATA file will do the trick.  
  
I'll have to find the best place to break the loop and synchronize the rest of the design.  
  
Thanks for quick answers!  
Best,  
Djordje

Answer

Hi DjordjeM,  
  
To add on kishoreataws's comment, Vivado has no knowledge of the design, so it simply scans for any existing combo path in the netlist. In addition, for example a SEU event on the register, might cause a misbehavior on the multiplexer select signal and therefore enable the combo path by accident. That's why it's not allowed to mitigate this error at the constraint level.  
  
One thing you could try is that if you're sure the combo path will NEVER be selected, or in other words,  enabled/utilized by the design, you could consider inserting a register to break the loop. Hope that helps.  
  
Thanks,  
  
- Chen

Answer

Dear customer  
  
Thank you for reaching out to AWS. Yes, F1 does not allow combinatorial loops and is documented in Errata  
https://github.com/aws/aws-fpga/blob/master/ERRATA.md  
  
Is combinatorial loops strictly required for your design and can not be addressed with other microarchitecture updates/design techniques?  
  
Thanks  
Kishore

Combinatorial Loop

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