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Use your own synthesis implementation strategy and constraints

0

Hi,

I am using aws-fpga vitis flow synth; I would like to add my synthesis/implemntation strategy and also placement constraints to package_kernel.tcl

Is it possible ? do you have any example ?

for instance to add user synthesis constraints for this example on aws-fpga; rtl_vadd?

https://github.com/Xilinx/Vitis_Accel_Examples/tree/f640bc8db1a9ffa8b09ae7b47ecca8b706132f75

Thanks

asked 8 months ago75 views
2 Answers
0
Accepted Answer

Hello,

You should be able to pass flags to v++ for your custom strategy and constraints. Xilinx provides the documentation here: https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/Managing-Vivado-Synthesis-and-Implementation-Results

In the Vitis examples, you should be able to add them to VPP_FLAGS.

Please let us know if that doesn't work for you.

-Deep

answered 8 months ago
  • Hey Deep,

    Thanks for your help; I create file which was added into the v++ synthesis path; The file contains the folloiwng:

    vivado prop=run.synth_1.STRATEGY=Flow_PerfOptimized_high prop=run.impl_1.STRATEGY=Performance_ExplorePostRoutePhysOpt

    I synthesis the entire flow and v++ later on exit with error:

    What I see is relevant that the error: caught error: problem implementing dynamic region Is it becuase I am using PhysOpt strategy ?

    Please advise Thanks

    ERROR: VPL_TCL 101-2 design did not meet timing - hold violation ERROR: VPL_TCL 101-3 sourcing script /home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/scripts/_full_post_route_phys_opt_post.tcl failed INFO: Common 17-206 Exiting Vivado at Sun Feb 20 05:15:59 2022...

    01:51:45 Starting bitstream generation.. Starting optional post-route physical design optimization. 02:15:36 Phase 1 Physical Synthesis Initialization 02:23:12 Phase 2 Critical Path Optimization 05:15:59 Run vpl: Step impl: Failed 05:16:01 Run vpl: FINISHED. Run Status: impl ERROR

    Please advise Thanks

0

Hey Deep,

Thanks for your help; I create file which was added into the v++ synthesis path; The file contains the folloiwng:

[vivado] prop=run.synth_1.STRATEGY=Flow_PerfOptimized_high prop=run.impl_1.STRATEGY=Performance_ExplorePostRoutePhysOpt

I synthesis the entire flow and v++ later on exit with error:

What I see is relevant that the error: caught error: problem implementing dynamic region Is it becuase I am using PhysOpt strategy ?

Please advise Thanks

ERROR: [VPL_TCL 101-2] design did not meet timing - hold violation ERROR: [VPL_TCL 101-3] sourcing script /home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/scripts/_full_post_route_phys_opt_post.tcl failed INFO: [Common 17-206] Exiting Vivado at Sun Feb 20 05:15:59 2022...

[01:51:45] Starting bitstream generation.. Starting optional post-route physical design optimization. [02:15:36] Phase 1 Physical Synthesis Initialization [02:23:12] Phase 2 Critical Path Optimization [05:15:59] Run vpl: Step impl: Failed [05:16:01] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while Compiling (bitstream) accelerator binary: rna.link Log file: /home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/impl_1/runme.log : **ERROR: [VPL 101-2] design did not meet timing - hold violation ERROR: [VPL 101-3] sourcing script /home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/scripts/_full_post_route_phys_opt_post.tcl failed **ERROR: [VPL 60-773] In '/home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/runme.log', caught Tcl error: problem implementing dynamic region, impl_1: phys_opt_design (Post-Route) ERROR, please look at the run log file '/home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation. ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: phys_opt_design (Post-Route) ERROR, please look at the run log file '/home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information ERROR: [VPL 60-1328] Vpl run 'vpl' failed ERROR: [VPL 60-806] Failed to finish platform linker INFO: [v++ 60-1442] [05:16:01] Run run_link: Step vpl: Failed Time (s): cpu = 00:09:19 ; elapsed = 12:21:22 . Memory (MB): peak = 2006.000 ; gain = 0.000 ; free physical = 33820 ; free virtual = 66867 ERROR: [v++ 60-661] v++ link run 'run_link' failed ERROR: [v++ 60-626] Kernel link failed to complete ERROR: [v++ 60-703] Failed to finish linking INFO: [v++ 60-1653] Closing dispatch client. make: *** [build_dir.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/rna.xclbin] Error 1

ERROR: caught error: problem implementing dynamic region, impl_1: phys_opt_design (Post-Route) ERROR, please look at the run log file '/home/centos/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/rtl_kernels/rtl_rna/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information [05:15:59] Run vpl: Step impl: Failed INFO: [OCL_UTIL] current step: vpl.impl failed. To rerun the existing project please use --from_step vpl.impl problem implementing dynamic region, impl_1: phys_opt_design (Post-Route) ERROR, please look at the run log file '/home/centos/src/project_data/aws-f

answered 8 months ago

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