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Hi Ismael,
Could you share some more information on the design you're planning to implement? Do you plan to implement a DMA for the Host -> FPGA over PCIS as well as a DMA for FPGA -> Host over PCIM?
Thanks!
-Joe
Hello,
Thank you for reaching out to AWS with your question. The S_AXI_PCIM interface provides a way for the Customer Design to initiate PCIe transaction cycles to the Host memory. The interface supports full AXI4 protocol with 512-bit wide datapath. Customers can easily interface their kernel, custom DMA, Xilinx IP with AXI4, etc, to S_AXI_PCIM interface to reach Host Memory.
AWS provides Streaming Data Mover, a custom Data Mover with AXI4-to-AXIS conversion to move data between FPGA and Host. Important links regarding SDE below:
Example CL design using SDE IP
Please note, while the S_AXI_PCIM and above SDE IPs allow customer design to access host memory directly, they require Physical Memory Address of the Host and not the virtual memory address. Please refer to your Operating System details for Virtual-to-Physical Memory Address Translation.
Please let us know if you have any questions.
Thanks!
Chakra
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