How many DRAM channels are needed to saturate the PCIe bandwidth on F1?

Hello,

I'm an image processing researcher and I am interested in using Vitis on the F1 to accelerate some applications. All of these applications will read in streams of 1920 x 1080 images and write out 1920 x 1080 images. The total amount of data read will be the same as the total amount of data written, and the images will be loaded in raster-scan order (one row at a time). The applications are easy to parallelize and can be fully pipelined, so that in their steady state they can accept new data every cycle and write finished data every cycle.

My understanding is that the connection between the FPGA and its memory is PCIe 3.0 x16, and that the peak bidirectional bandwidth is approximately 32 GB / sec (16 GB / sec of writes and reads respectively).

From reading other questions / documentation I gather that there are four DRAM channels, each with a peak bandwidth of 17 GB / sec (https://forums.aws.amazon.com/thread.jspa?threadID=269319).

Am I understanding the PCI and DRAM bandwidth correctly? And if so can a Vitis application reach the peak bandwidth of the PCIe connection by using only 2 of the 4 DRAM channels (one for reads and one for writes).

Thanks in advance!