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Hi,
Yes, F1 Instances have PCIe gen3 x16 Link between the FPGA and the Host, with FPGA as PCIe endpoint. So theoretically PCIe link should supports max bandwidth of 16GB/s per direction. However due to system latencies and other overheads, the design may not be able to hit the theoretical max. In F1, max achievable bandwidth is also dependent on the Custom Design (CL) as well.
You will still be able to achieve max bandwidth using only one DRAM channel. Following are few other posts that may help you:
https://forums.aws.amazon.com/thread.jspa?messageID=818846󇺞
https://forums.aws.amazon.com/thread.jspa?messageID=812716󆚬
https://forums.aws.amazon.com/thread.jspa?messageID=940247󥣗
https://forums.aws.amazon.com/thread.jspa?messageID=897261󛃭
https://forums.aws.amazon.com/thread.jspa?messageID=846147󎥃
Please contact us if you need any additional details.
Thanks!
Chakra
Thanks Chakra!
You mentioned that it will be possible to reach peak bandwidth with only 1 DRAM channel. So is it correct to say that the unidirectional bandwidth of one DRAM channel is ~17 GB/sec, and that each channel supports 17 GB/sec per direction?
Hello,
The DDR data pins are shared between read and write accesses. Therefore, the max available DDR bandwidth of ~17GB/s is shared between reads and writes. You can potentially achieve maximum performance when your accesses are either write-only or read-only.
Please let us know if you seek additional details.
Thanks!
Chakra
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