SIGSEGV error during simulation.

Question

While compiling my desing with the latest version of HDK Kit (HDK_VERSION=1.4.7) and Vivado version 2018.2, I get the following error.   
ERROR: \[XSIM 43-3316] Signal SIGSEGV received.  
  
I also found another user having the same error with an hdk example design itself as in thread below.  I am attaching tail my elaborate.log below to provide another datapoint.  
https://forums.aws.amazon.com/thread.jspa?messageID=890695&#890695  
  
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WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:475]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:476]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:477]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:478]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:479]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:480]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:481]  
WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:482]  
WARNING: \[VRFC 10-727] function device_bdr_ld has no return value assignment \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:396]  
WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2527]  
WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2685]  
WARNING: \[VRFC 10-727] function match_char_after has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4562]  
WARNING: \[VRFC 10-727] function match_range has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4575]  
WARNING: \[VRFC 10-727] function track_value_context has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:5545]  
WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1571]  
WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1573]  
WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:182]  
WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:195]  
WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:117]  
WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:118]  
WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/len_model_mgmt.sv:320]  
WARNING: \[VRFC 10-597] element index 16 into valid_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:147]  
WARNING: \[VRFC 10-597] element index 16 into sign_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:148]  
WARNING: \[VRFC 10-597] element index 16 into dividend_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:149]  
WARNING: \[VRFC 10-597] element index 16 into dividend_lo_bits_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:150]  
WARNING: \[VRFC 10-597] element index 16 into divisor_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:151]  
WARNING: \[VRFC 10-597] element index 16 into remainder_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:152]  
WARNING: \[VRFC 10-597] element index 16 into quotient_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:153]  
WARNING: \[VRFC 10-597] element index 16 into division_done_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:154]  
Completed static elaboration  
WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 855 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.  
WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1753 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored.  
INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2527, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv  
INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2685, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv  
ERROR: \[XSIM 43-3316] Signal SIGSEGV received.  
"elaborate.log" 159L, 29695C

fpgamagic · Answer

I found the cause for this issue. I isolated the module causing this error and compiled separately. I found that this module had some warnings regarding functions not having defined the return values. After fixing those, this error went away.

SIGSEGV error during simulation.

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