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3D RAM as register

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I am creating a 3 D signal as shown below and I understand that this would be implemented as register.
"logic \[N-1:0]\[N-1:0]\[1:0] X;"

But When I run synthesis with N=64 it works perfectly while for N=128, synthesis is stuck at warning as shown below. Is it too much large number of registers to run on vertex ultrascale plus FPGA ?

"WARNING: \[Synth 8-5856] 3D RAM X_reg_reg for this pattern/configuration is not supported. This will most likely be implemented in registers"

How can I know numbers of block RAM instances and their characteristics (such as maximum width etc) is supported by particular F1 instance ?

Edited by: aiquanta on Jul 18, 2021 4:49 AM

Edited by: aiquanta on Jul 18, 2021 4:49 AM

Edited by: aiquanta on Jul 18, 2021 4:50 AM

Edited by: aiquanta on Jul 18, 2021 4:51 AM

Edited by: aiquanta on Jul 18, 2021 4:51 AM

asked a year ago54 views
1 Answer
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Hi aiquanta,

Xilinx publish detailed information on primitives supported by a specific device architecture in its architecture libraries guide. Here is an example: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug974-vivado-ultrascale-libraries.pdf. Most time, you should be able to find answers from this document. Xilinx forum will be another good source for finding this type of information. Regarding to the warning [Synth 8-5856], I think you're right. By switching to 128, it's very likely that it breaks some implicit rules set for the maximum BRAM cascading number or something similar.

In addition, I would strongly recommend you to follow the Xilinx's guidance on the coding style for primitive inference (Here is a reference, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug974-vivado-ultrascale-libraries.pdf). There is a small chance sometimes the synthesizer might not be able to interpret the code correctly. It would be good to avoid that as much as possible. Hope this helps you.

Thanks,

  • Chen
answered a year ago

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