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Synthesis & CSim hangs on Vitis HLS GUI

0

Hi. This is a follow-up question to: https://forums.aws.amazon.com/message.jspa?messageID=990108#990108
I am using Vitis HLS GUI on AWS M5.xlarge instance with FPGA Developer AMI 1.10.0
I am currently in Los Angeles and logging into N. California AWS server, so latency shouldn't be too bad.

I create a simple project with source files which I know synthesized correctly in my own servers with Vitis HLS 2020.2.
But when I pressed "Synthesis" (the green arrow button) or when I pressed CSim (in the pull-down menu),
Vitis HLS simply hangs and does not respond.
No error message - simply hangs. The program itself is not dead - it does accept other commands, such as switching to Debug tab.

Could anyone help me solve this problem?

Topics
Compute
Tags
FPGA Development
Language
English
asked 5 years ago500 views
2 Answers
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Hi Young,

I'll check with Xilinx on this. Are there any logs that you can share?

-Deep

answered 5 years ago
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Thanks. Actually, I decided to use NICE DCV as you suggested, and that flow does not have this problem. Thanks for clarifying that it is free of use :)

answered 5 years ago

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