How do I check the clock recipe that an awsxclbin was built with?

Hi Bhagath,

The create_vitis_afi.sh script is provided to facilitate the AFI generation. If you refer to it: https://github.com/aws/aws-fpga/blob/master/Vitis/tools/create_vitis_afi.sh#L212-L214, you can see how Vitis names the clocks and connect them to the clocks provided by the shell.

Please note Vitis kernel can select from either the DATA_CLK (default) or the KERNEL_CLK clock. The selection can be done using the "kernel_frequency" option during the v++ link stage. See here for more details:
https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitiscommandcompiler.html#qcm1528577331870__section_frk_xtr_t3b

The reason you saw different clock frequency than the ones listed in the clock recipe is because of frequency scaling. Vitis will tune down the clock frequency if the target frequency cannot be achieved with the given kernel design. For more details, please refer to https://www.xilinx.com/support/documentation/sw_manuals/xilinx2021_1/ug1393-vitis-application-acceleration.pdf

By default, these are the frequencies of the clocks provided in the F1 platform:

SYSTEM = clock_main_a0=250
DATA_CLK = clock_extra_b0=250
KERNEL_CLK = clock_extra_c0=500

I hope this helps.

Thanks,

Chen

Hi,
Once you run the create_vitis_afi.sh script, the manifest file is created, which contains the clock freq that vitis used to meet timing.
Thanks
Kris

Hi,

When I look at the manifest file, it has 3 different frequencies listed. Can you give some more details about what they are used for?

clock_main_a0=250
clock_extra_b0=233
clock_extra_c0=500

Thanks
Bhagath

Hi Bhagath,

It's that shell provides extra flexibility by feeding multiple frequencies to the customer design in case part of a design requires multiple clocks, for example, for performance or timing closure reasons. Please refer to the link below for details:

https://github.com/aws/aws-fpga/blob/4750aacb4dac9d464b099b27e4337220cf0b0713/hdk/docs/AWS_Shell_Interface_Specification.md#clocks

Thanks,

Chen

Hi Chen,

Thanks for the reply.
But I am still not sure about where exactly in my logic is the clock_extra_c0 is being used. It says the KERNEL Frequency is 500 MHz in the Vitis analyzer when I open up the run summary file which gets generated after running an inference. Does it mean that the Kernel is executed at 500 MHz?
Even though I see that clock_extra_c0=500 in the manifest file, There is no option for 500 MHz in the Clock Group C given in the documentation. How is this possible?

Also, I noticed that the "clock_extra_b0=233 MHz" in the manifest file that got generated. However, there is no option of 233 MHz for clocks listed in the clock_recipies.csv file given in the documentation.

Thanks
Bhagath

Hi Bhagath,

Sorry for the slow response on this post. I want to let you know that we're still working with Xilinx in order to provide the details you're asking. We will keep you posted as soon as we hear back from Xilinx.

Thanks,

Chen