Create DCP encounter port missing
Hello:
I use aws-fpga f1_xdma_shell branch to implement aws_create_dcp_from_tcl flow to get dcp and tar file, and it seems that the flow has finished synthesis and inplementation (also dcp file has been generated).
However, there has a missing port error shown in attachment picture, and caller_combined_wrapper is our design and I think cl_simple_bb may be some cl built-in aws-fpga? I just can't find where are the cl_simple_bb in library work_cl_cl_1 with NOFILE(?) and caller_combined_wrapper.edf
Moreover, the missing port shown are about CLK_300M_DIMM_0_DP, CLK_300M_DIMM_0_DN, ..., and I find these port in common/shell/build/constraint/cl_ddr.xdc constraint file, so I replace these port names with our design DDR I/O port, but run the create_dcp process still has same issue
Thank you!!
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It appears you're encountering an issue with missing ports while trying to create a Design Checkpoint (DCP) for an AWS FPGA F1 instance using the aws-fpga f1_xdma_shell branch. The error suggests that there are missing connections for certain clock ports (CLK_300M_DIMM_0_DP, CLK_300M_DIMM_0_DN, etc.) in your design.
This issue could be related to how your custom design (caller_combined_wrapper) is interfacing with the AWS Shell. The cl_simple_bb mentioned in the error message is likely a part of the AWS FPGA shell infrastructure.
Replacing the port names in the cl_ddr.xdc constraint file with your design's DDR I/O ports may not be the correct approach, as these constraints are typically part of the AWS Shell and should not be modified directly.
To resolve this issue, you should ensure that your custom design (caller_combined_wrapper) properly interfaces with the AWS Shell. This includes:
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Verifying that your design correctly implements the required interface signals as specified in the AWS FPGA documentation.
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Checking that all necessary ports are declared and connected in your Verilog code (caller_combined_wrapper.v).
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Ensuring that you're using the correct clock domains and signals as provided by the AWS Shell.
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Reviewing the AWS FPGA documentation for any specific requirements or guidelines for interfacing with the DDR memory subsystem.
If the issue persists after verifying these points, you may need to seek further assistance from AWS FPGA development forums or AWS support, as this could indicate a more complex integration problem between your design and the AWS FPGA infrastructure.
Sources
FPGA F2 development issue | AWS re:Post
answered a year ago
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