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F1 FPGA LUT utilization target

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My design is consumes ~55% LUTs. The RAM and DSP utilization is pretty low < 10%. When I try add more logic it runs into congestion issues. So, I am trying to reduce some bus widths. However, I would like to know if there is a good rule of thumb on what LUT utilization can be target without hitting congestion issues. I am hoping you guys have such data from various customer datapoints. Thanks

asked 8 months ago26 views
2 Answers
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Hi @AWS-agdp, I wanted to check in case the conversation on our aws-fpga Github is the same one you are asking for here? If not, please let us know and I can get more details.

-Deep

answered 8 months ago
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Yes it is the same question and it has been answered. Thanks

answered 8 months ago

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