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Hi,
Yes, the DDR Controller provided by AWS in sh_ddr.sv is a Xilinx IP that is hard configured to perform auto-precharge when axi_addr[8] is set. This is beneficial for sequential access patterns, but it can be inefficient for random access patterns.
Unfortunately, as of now, we do not have support for user configurable DDR Controllers. Having said that, please feel free to provide any details on your desired use-case and configurations if possible. I will be happy to provide this feedback for the team internally.
Thanks!
Chakra
Hi Chakra,
Thanks for your reply. It's a pity that the setting cannot be changed. I'm building an accelerator for large-scale graph analytics and some of the DDR accesses are single-beat and irregular, which would benefit from a closed-page policy. I was also considering to use our throughput-oriented memory controller ( https://www.epfl.ch/labs/lap/wp-content/uploads/2020/03/CsordasDec19_InSearchOfLostBandwidthExtensiveReorderingOfDramAccessesOnFpga_ICFPT19.pdf ) that reorders requests on a much larger scale than general-purpose controllers to maximize the row hit rate, but that would require an open-page policy or, at least, a reasonably simple policy that is not dependent on the access pattern.
Best regards,
Mikhail
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