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Hello fpgamagic,
I guess you have missed the poke_stat routine. That releases the reset to the DDR B.
// tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000));
tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000));
//tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000));
Add this before the peek_bar routine and you should see that ddrb_is_ready is asserted after the delay.
Regards
Bala
answered 5 years ago
0
@awsbalasram Thanks. I found and ended up adding tb.init_ddr() to my routine. Which basically includes exactly the statements pointed out by you. After this I can confirm that the ddr_is_ready signal goes up.
Thanks
fpgamagic
answered 5 years ago
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