Problem instanciating ILA in TCL workflow

Question

Hello.  
  
I am trying to add an ILA to check the behavior of an AXI bus in my design.  
My design works in simulation but gets stuck on the FPGA. In order to debug this I want to check an AXI bus with an ILA.  
  
I used the following document as a reference :   
  
And the "hello_world" design as an example.  
  
I instanciated the debug bridge in my top with the following lines :

```
        // Debug Bridge
        cl_debug_bridge CL_DEBUG_BRIDGE (
            .clk(clk_main_a0),
            .S_BSCAN_drck(drck),
            .S_BSCAN_shift(shift),
            .S_BSCAN_tdi(tdi),
            .S_BSCAN_update(update),
            .S_BSCAN_sel(sel),
            .S_BSCAN_tdo(tdo),
            .S_BSCAN_tms(tms),
            .S_BSCAN_tck(tck),
            .S_BSCAN_runtest(runtest),
            .S_BSCAN_reset(reset),
            .S_BSCAN_capture(capture),
            .S_BSCAN_bscanid_en(bscanid_en)
        );
```

I created an ILA using the IP catalog and a board diagram, the board diagram is because the ILA names the input ports probeXX instead of the AXI signal names and with the board diagram I can make a wrapper with the correct names.  
  
I added the ILA in the design and got the following errors on synthesis :

```
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Vivado_Tcl 4-550] User specified maximum number of URAM that can be cascaded is 2
CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_in.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results:
* bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_in.vh)
* test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_in.vh)
Please reset and regenerate these modules to resolve the differences, or synthesize them independently.
CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results:
* bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs.vh)
* test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs.vh)
Please reset and regenerate these modules to resolve the differences, or synthesize them independently.
CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs_core.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results:
* bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_core.vh)
* test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs_core.vh)
Please reset and regenerate these modules to resolve the differences, or synthesize them independently.
CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_vl_rfs.v' is used by one or more modules, but with different contents, and may lead to unpredictable results:
* bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v)
* test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v)
Please reset and regenerate these modules to resolve the differences, or synthesize them independently.
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 17187 
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5838]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5867]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5900]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5934]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9887]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9916]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9949]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9983]
Failed to read verilog '/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v'
INFO: [Common 17-83] Releasing license: Synthesis
6 Infos, 17 Warnings, 4 Critical Warnings and 9 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

while executing
"source -notrace ./synth_${CL_MODULE}.tcl"
    invoked from within
"if {${cl.synth}} {
   source -notrace ./synth_${CL_MODULE}.tcl
}"
    (file "create_dcp_from_cl.tcl" line 196)
INFO: [Common 17-206] Exiting Vivado at Mon May 27 15:52:58 2019...
```

There is a conflict between the sources used by the debug bridge IP and my ILA IP.  
I followed the instructions in  Embedding Debug Cores in the CL. But I could not find how to solve this.  
  
Do you have any suggestion on how to solve this ?  
Thank you very much. Best Regads.

Answer

Hello,  
I will try modifying and using the ILAs that were provided.  
  
I need to modify them to change the number of ports, as well as their size.  
I will report on this next week. Thank you.

Answer

Hello,  
Were you able to resolve this issue ?  
  
Thanks

Answer

Hello.  
I can build the hello world example.  
  
I used the ILA version 6.2 from the IP catalog. I did use Vivado 2017.4 to generate it.  
  
I use Vivado 2018.3 to build the project, several IPs are still from Vivado 2017.4 because they were created in older projects. The version of the CL shell I use is v04261818, HDK ver 1.4.8.  
  
I did not try any IPI example or flow.

Answer

Yes,  
Using and modifying the existing ILA core did work. Thank you.  
  
Regards.

Answer

Ok, thanks for confirming the hello world plus debug is working.    
Instead of generating ILA, please try to use the IP (ILA and debug bridge) included in the developer kit.    
https://github.com/aws/aws-fpga/tree/master/hdk/common/shell_v04261818/design/ip

Answer

Hi,  
  
Does the aws-fpga hello world example with debug work for you?    
  
Have you tried adding debug to the IPI hello world example?  
  
For your design, "ILA using the IP catalog and a board diagram", What version of the ILA did you use?  The versions the example use are located:  https://github.com/aws/aws-fpga/tree/master/hdk/common/shell_v04261818/design/ip/  
  
What version of the tools are you using?  
  
Thanks  
Kris

Problem instanciating ILA in TCL workflow

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