I am assuming your design uses PCIS interface from Shell to provide datapath to the Host Memory. Our example CL_DRAM_DMA has this datapath where PCIS interface feeds an interconnect which then connects to all four DDR. Host can access the PCIS interface (and hence the DDR) through PF0 BAR4 address exposed to the Host as shown below:
AWS provides peek/poke APIs to access the PF/BARs from the host. You should be able to access PF0-BAR4 using APIs below:
Please let us know if you run into any issues or have any questions.
I was able to access either FPGA's BAR4.
Thanks for pointing to the API's and doc.
Single kernel argument getting access to multiple DDR banks.
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