Timing failure in dbg_hug after enabling DDRA in cl_hello_world_ref_hlx ex

Seeing a intra-clock timing violation between clocks "rdck" and "tck" (both associated by dbg_hub) after enabling DDRA and connecting a CDMA IP to it.

Notes:

1. dbg_hub is automatically added by vivado.
2. Getting Critical Warnings when vivado processes file "cl_debug_bridge_hlx.xdc"
3. Added false clock path between drck and tck to "cl_synth_user.xdc" has no effect.
4. Using Vivado 2020.1 and Shell shell_v04261818

I realize that by adding DDRA, I am adding debug that comes with the DDR PHY so my guess is there is an issue with the constraints in file "cl_debug_bridge_hlx.xdc"???

Has anyone ever run into this ?

Thanks
Brian