Looking for example using Vitis with RTL CL and DDR ram

Hello,

You can find example of RTL kernels in the Vitis flow here:
https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/rtl_kernels
I suggest starting with the simple rtl_vadd design.

A few high-level things to understand:

• RTL kernels need to comply with specific interface rules
• RTL kernels are Vivado IP blocks, packaged as .xo files for Vitis
• In the Vitis flow, the user doesn't need to explicitly manage DDRs, instead you simply specify which DDR you want to connect your kernel ports to and the v++ linker takes care of the rest.

More details in the Vitis docs:
https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk2020182740.html#qnk1504034323350
https://www.xilinx.com/html_docs/xilinx2019_2/vitis_doc/Chunk2086915788.html#ariaid-title6

Thanks - that makes sense. I was able to create a .xo file in Vivado 2019.2 locally from a RTL project using the example design, is it possible for me to copy one of the aws example folders and modify the Makefile to include my .xo? (e.g. modify BINARY_CONTAINER_vadd_OBJS in Vitis_Accel_Examples/hello_world/Makefile) and it will link OK?

I also tried to make a Vitus project locally but had issues getting the platform to load from https://github.com/aws/aws-fpga/tree/master/Vitis/aws_platform/xilinx_aws-vu9p-f1_shell-v04261818_201920_1 , do I need to first build this using vitis_setup.sh and then I can copy the platform files locally?

You can indeed copy one of the examples and reuse the Makefile, but I think it is a little overkill. These Makefiles are built to support many different plaforms and have a lot embedded intelligence which is not needed if you only target F1. You can do a "make <your options> -n" to see what commands would really be executed and only reuse those. For instance, the hello_world example Makefile will compile the C kernel (v++ -c). You probably don't want to do this since you already have your .xo. Unless you are combining multiple .xos, then the only thing you need to do at this point is run the v++ linker (v++ -l). Keeping things simple will help you better understand the flow and gradually take advantage of Vitis features.

If you want to work locally, then you need to clone the aws-fpga repo and then source vitis_setup.sh. This will download the platform .xsa file which is not hosted on the repo.

Ok makes sense, thanks for your help.