- Newest
- Most votes
- Most comments
Hello JWadden,
Could you please let us know which HDK version you are using ?
You mentioned "recent set of innocuous modifications to the source", is it possible that after reverting these changes you are able to synthesize successfully ?
--Thanks
Siddharth
I just updated to HDK 1.4.7 and got the same synthesis errors. It attempted to install patch AR71715. Vivado's output looks like the following:
INFO: Setting up environment variables
INFO: Base vivado version is Vivado v2018.2_AR71275_op (64-bit) ; Checking if patch AR71715 needs to be installed
INFO: SDX patch AR71715 is valid for Vivado v2018.2_AR71275_op (64-bit)
INFO: Using Vivado v2018.2_AR71275_op (64-bit)
VIVADO_TOOL_VERSION is v2018.2
INFO: Using HDK shell version shell_v04261818
INFO: HDK shell is up-to-date
INFO: HDK shell is up-to-date
INFO: HDK shell is up-to-date
INFO: DDR4 model files in /home/centos/r/aws-fpga/hdk/common/verif/models/ddr4_model/ were built with Vivado v2018.2_AR71275_op (64-bit)
INFO: CL_DIR is /home/centos/r/cl_basedir
INFO: AWS HDK setup PASSED.
I just clarified with a collaborator that we actually did not change the source before synthesis stopped working. Any thoughts?
-Jack
Hey,
We have run synthesis on cl_dram_dma example and do not see any issue with axi_register_slice_v2_1_15_axic_register_slice.
Is is possible to share your synthesis log file with us ? We will have a look at it.
-Thanks
awsSiddharth
Relevant content
- asked 3 months ago
- AWS OFFICIALUpdated 5 months ago
- AWS OFFICIALUpdated 2 years ago
- AWS OFFICIALUpdated 7 months ago
- AWS OFFICIALUpdated 7 months ago