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Loading of simulation waveform in Vivado is too slow

0

Hi,

I have been running a simulation in Vivado. Writing into the BRAM of 16 KB through PCIS is taking more than 2 hours. I need to write more than 10 BRAMS. If it takes time like this, I am worrying that I need to wait more than a day to simulate my design. Is it expected behaviour? Is there any way to reduce the simulation time?

Regards

Gogul

Topics
Compute
Tags
FPGA Development
Language
English

asked 2 years ago371 views

2 Answers
0

Hi Gogul,

This is kind of expected as 16KB is quite a "big" space to fill in simulation. If you're writing to BRAM to initialize it, one thing you can consider is to initialize BRAM through an external data file. There are many posts on AMD forum that you can refer to get an idea how to enable that. Hope that helps.

Thanks,

Chen

AWS

answered 2 years ago

  • GOGUL
    2 years ago

    Hi Chen, Thank you for your reply. I can use .coe files to initialize but I have different scenario. I am using Vivado's Block Design. In my Block Design I am using same module twice as Tx and Rx. Tx and Rx have to be loaded with different files. How can I achieve this?

0

Hi Chen,

Thank you for your reply. I can use .coe files to initialize but I have different scenario. I am using Vivado's Block Design. In my Block Design I am using same module twice as Tx and Rx. Tx and Rx have to be loaded with different files. How can I achieve this?

Regards

Gogul

answered 2 years ago

  • AWS-zhcz
    2 years ago

    Hi Gogul,

    That should be common to all widely used IPs. I image the 2 BRAM IPs will have different instantiation names and hierarchical locations. The .coe files should be associated with the individual instantiation not IP type. Hope that answers your question.

    Thanks,

    Chen

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