ERROR: [Synth 8-5809] Error generated from encrypted envelope, Failed to read verilog

Question

Hi,
I am new to AWS EC2 F1 FPGAs. I am trying to build cl_helloworld.sv example. When I am compiling synthesis failing due to following error.

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/aws-fpga/hdk/cl/examples/cl_hello_world/build/src_post_encryption/cl_hello_world.sv:470]
Failed to read verilog '/home/centos/aws-fpga/hdk/cl/examples/cl_hello_world/build/src_post_encryption/cl_hello_world.sv'
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 9 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

Could someone help to resolve this error?

Thanks,
Saichand

Answer

Hi Saichand,

I want to double check the branch you used for this job that generated the synthesis error. Since you're using Vivado v2022.1, you would need to switch to the branch "REL_2022_1" (https://github.com/aws/aws-fpga/tree/REL_2022_1) in order to build those CL examples. My guess is that you were using the main branch. If so, please switch the branch and try again. You should be unblocked.

In addition, please be careful about the memory error and the usage of the "-ignore_memory_requirement" option. Xilinx recommends at least 32GB memory space, so a bigger instance type is recommended.

Please let us know if you're still facing any problem.

Thanks,

Chen

Answer

Hi Saichand,

Thank you for your patience and all the information provided. That's very helpful. I'll further investigate this issue on my end to see if I can replicate this. I'll keep you updated asap.

Thanks,

Chen

Answer

This error message suggests that there's an issue with the encrypted envelope for the cl_helloworld example in AWS EC2 F1 FPGA. It seems like the encrypted Verilog file failed to be read during synthesis, causing the synth_design process to fail.

To resolve the issue, you could try the following steps:

* Check the file path of the encrypted Verilog file to ensure it's correct and readable.
* Check the permissions of the file and the directories to ensure they are set correctly.
* If the file path is correct and the permissions are set correctly, try re-encrypting the Verilog file.
* If re-encrypting doesn't work, try to compile a different example to see if it's a general issue with the AWS EC2 F1 FPGA setup or just with this specific example.

Answer

Hi Saichand,

Thank you for being interested in F1 instance. Divyam has really good points. Can you please check those points and make sure you see the encrypted cl_hello_world.sv under /src_post_encryption. I recommend you double check and ensure that you are following the steps here (https://github.com/aws/aws-fpga/tree/master/hdk#getting-started) for building the cl_hello_world example. In addition, can you please let me know if you're running this test on a EC2 instance or on an on-prem machine?

Thanks,

Chen

ERROR: [Synth 8-5809] Error generated from encrypted envelope, Failed to read verilog

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