Inquiry About Vitis AFI Generation Support on f2/vitis Branch

Hi ywvec,

XRT

On F2, the XRT currently supports Hardware Emulation. Full hardware, AFI building and running are the next feature we're working on for Vitis!

As for your question about register access: yes! The fpga_pci_peek/poke() functions are the way to go for accessing individual registers within your design.

XDMA

Features using the XDMA engine are not currently supported on F2. We're working to get this feature available as quickly as possible.

In the meantime, I encourage you to look at the example cl_sde, which uses the Streaming Data Engine, SDE and the small shell, in order to transfer data to and from the FPGA's DDR4, HBM, and register space, which you've defined.

The SDE offers data transfer capabilities on par with the XDMA engine. This will allow you to build a design with a performant mechanism for transferring data to and from the host.

Best, Max

Hi ywvec,

1. axi_mstr_addr_access() does allow you to write to DDR using the AXI master block, but it isn't a high-speed mechanism. That's because it takes several register accesses to then perform a single DDR access. The best performance will be achieved by using the SDE, linking it to your memory to allow DMA and large block transfers.

2. That's right and this is how other customers are currently using the SDE! The SDE is itself a DMA engine and will therefore work off of the AXI bus that connects from the PCIe IP to the shell interface.

3. That's correct. cl_sde is a minimal example showing a data loopback, rather than being connected to HBM or DDR. However, the design can be extended to connect to either!

Best, Max

I apologize, but I don't have specific information about official support or release dates for AFI generation using Vitis workflows on F2 instances. The development of new features and updates for AWS FPGA services is an ongoing process, and release timelines are not publicly available.

Regarding the use of custom HLS IPs created with Vitis HLS, the current F1 instances do support FPGA development using various tools and environments, including C/C++ and OpenCL. While I can't provide specific workarounds for integrating Vitis HLS IPs into existing flows, developers can use the FPGA Developer AMI provided with F1 instances. This AMI includes development tools for simulating, building, and registering AFIs without additional software charges.

For the most up-to-date information on FPGA development capabilities and supported workflows, I recommend checking the official AWS documentation or reaching out to AWS support directly. They would be best positioned to provide guidance on current capabilities and any upcoming features related to Vitis support on F2 instances.
Sources
F2
Amazon EC2 F1 Instances

Hello!

While I can't share a timeline for release, I can say that Vitis AFI generation is the next feature slated for release on the Vitis roadmap.

In the meantime, I recommend starting your design by using Hardware Emulation to build, simulate, and iterate on your design.

To your question about integrating Vitis HLS IPs in to existing flows, have you already created this IP and are looking to integrate it into your current design, or do you want to know how to create a new Vitis HLS IP?

Best, Max (AWS FPGA Team)

Hi Max,

Thank you again for your quick and helpful response.

Yes — I already have existing HLS IP that I need to integrate into a design targeting AWS F2. Given the current status of Vitis AFI generation, could you advise which development flow is best suited for this use case? Would the traditional HDK flow be the recommended approach for now?

If so, I’m planning to use the cl_dram_hbm_dma Custom Logic example as a starting point: https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma

I have two specific questions related to this:

1. Controlling HLS IP registers

What is the recommended way to access and control internal registers within an HLS IP (e.g., for configuration or status reporting)? I’d like to understand how to properly integrate and interact with these registers in the context of the HDK framework.

2. Transferring data from host to F2 memory

I would like to transfer files (e.g., image or text files) from the host to either DDR or HBM on the F2 instance. What is the best practice for handling such data transfers in the current supported development flow?

Any documentation, examples, or general guidance would be greatly appreciated.

Best regards, ywvec

Hi ywvec,

You can still use Vitis to meet your needs at present! Hardware Emulation allows you to build your design and simulate it, IPs included.

If you're interested in moving over to the HDK flow, note that it will be a pure RTL-based flow. In this case, you would need to export your Vitis HLS IP code for use in Vivado.

In the Vivado/HDK flow, you have the ability to define all aspects of the logic, according to your needs. This means that you could have a bank of registers that live at any address you like and they can represent any data in the layout of your choice.

With respect to data transfers, the simplest example for Vitis can be found here. This shows a simple block transfer from host memory to the FPGA's memory.

In the HDK flow, using cl_dram_hbm_dma as a reference point, you can see how burst data transfers are performed here!

That's then tied into the runtime examples here.

I hope this helps!

Best, Max (AWS FPGA Team)

Hi Max,

Thank you very much for the helpful information and references.

I have two follow-up questions:

1. Regarding the "simplest example for Vitis" https://github.com/Xilinx/Vitis_Accel_Examples/blob/main/hello_world/src/host.cpp#L80 you mentioned — I noticed that the host code is using XRT. From my understanding, XRT is not currently supported on AWS F2 instances. Is that correct?

2. As for the HDK flow, you mentioned that I can define registers at arbitrary addresses. In that case, would the recommended way to access those registers from the host be through the fpga_pci_peek() and fpga_pci_poke() functions provided in this library?

https://github.com/aws/aws-fpga/blob/f2/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c#L385

Thanks again for your support!

Best regards,

Hi Max,

Sorry for the consecutive posts, but I’m trying the following example on an AWS F2 instance: https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma

I was able to complete the process up to AFI generation and successfully loaded the AFI.

However, when I ran the test code located in https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_dram_hbm_dma/software/runtime,

I encountered the following errors and the test ended with "TEST FAILED":

test_dram_hbm_dma, ERROR, test_dram_hbm_dma.c +137: dma_example(): DMA write failed on iter: 0: error_number=512  
test_dram_hbm_dma, ERROR, test_dram_hbm_dma.c +83: main(): DMA example failed: error_number=512  
test_dram_hbm_dma, INFO, test_dram_hbm_dma.c +97: main(): TEST FAILED: error_number=512

The GitHub README includes the following statement: "Features using XDMA engine are currently unsupported on F2 instances"

Does this mean that XDMA is not supported on F2 instances?

If XDMA cannot be used, could you please advise on alternative methods to access DDR4 or HBM on the FPGA?

Thank you in advance for your support.

Best regards, ywvec

Hi Max,

Thank you very much for your detailed and helpful answers.

I have a few more questions regarding cl_dram_hbm_dma and cl_sde:

1. In the software for cl_dram_hbm_dma, I saw that the axi_mstr_addr_access() function can be used to access DDR4 and HBM: https://github.com/aws/aws-fpga/blob/f2/hdk/cl/examples/cl_dram_hbm_dma/software/runtime/test_dram_hbm_dma.c#L304 It looks like this is done by controlling internal registers of the RTL module cl_dram_dma_axi_mstr. Would it be possible to use this module to achieve high-speed access to DDR4 or HBM, similar to XDMA?

2. When thinking about host-to-DDR4 transfers, I imagined a design where the AXI-Stream bus from the SDE is connected to an AXI DMA IP to write to DDR4 or HBM. Is this aligned with your vision of how SDE-based data movement should be handled?

3. From what I understand, the current cl_sde example does not connect to either DDR4 or HBM. Is that interpretation correct?

Thanks again for your support — your guidance is very helpful!

Best regards, ywvec

Hi Max,

Thank you for your reply.

First of all, we’ll try integrating our IP using the cl_dram_hbm_dma design as a starting point. If we encounter performance limitations with that approach, we’ll definitely look into using the SDE for higher-speed data movement.

Thanks again for all the valuable information. Also, I’m looking forward to the next release of the AWS FPGA Development Kit!

Best regards, ywvec