XDMA transfer fails when writing to BRAM, Peek/Poke also not functional

Hi,

Please see our answers below:

1. Any reason why I'm not successful in read/write over XDMA to BRAM (DDR operations are successful)?
   AWS From your design/addr space, I see that DDR is on PCIS-BAR and BRAM Controllers are on OCL interface. Please note that OCL is 32-bit AXI-Lite Interface, and PCIS is 512-bit AXI4 Interface. Please ensure AXI Interconnect supports both. The XDMA (DMA Engine) is mapped to transfer data through PCIS Interface, therefore you see data transfers to DDR but not to BRAM. Please connect/define address space for BRAM in the PCIS range and it should work.

2. Why is Peek/Poke failing?
   AWS Did you try using the PCIe APIs provided by AWS? Useful links below:
   -- https://github.com/aws/aws-fpga/blob/master/sdk/userspace/fpga_libs/fpga_pci/fpga_pci.c#L337
   -- https://github.com/aws/aws-fpga/blob/master/hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c#L324

3. Should I be able to use Peek/Poke over PCIS interface (not in the same time when using PCIS for XDMA), or should I use OCL instead?
   AWS Yes, you should be able to use peek/poke access to PCIS (even when XDMA is in operation). Please note, that these two are queued internally and can impact latency when both are active.

4. Please refer to the following information for non-root access to FPGA
   https://github.com/aws/aws-fpga/tree/master/sdk#using-fpga-as-non-root-user

Please reach us if you need any additional details.

Thanks!
Chakra

Edited by: awschakra on May 18, 2021 11:31 AM

Hello Chakra,

thank you very much for your answers! I figured out I was stupid when setting up address map and therefore my reads/writes were failing.

Can I please ask you one more thing:

Please note that OCL is 32-bit AXI-Lite Interface, and PCIS is 512-bit AXI4 Interface. Please ensure AXI Interconnect supports both.  

Can you explain further on how to "ensure" this? I set "register slice" option for every slave and master interface to "Auto". Also, Fifo Depth for each interface is set to 32. Should I do anything else, or should this be enough?

Hello Chakra,

thank you very much for your answers! I figured out I was stupid when setting up address map and therefore my reads/writes were failing.

Can I please ask you one more thing:

Please note that OCL is 32-bit AXI-Lite Interface, and PCIS is 512-bit AXI4 Interface. Please ensure AXI Interconnect supports both.  

Can you explain further on how to "ensure" this? I set "register slice" option for every slave and master interface to "Auto". Also, Fifo Depth for each interface is set to 32. Should I do anything else, or should this be enough?

Hello,

Apologies for delayed relayed response on this post.

Since you are connecting OCL and PCIS bus to the interconnect, I would make sure that the AXI Crossbar/Interconnect IP handles two masters with different AXI protocols -- AXI-Lite for OCL, and AXI4 for PCIS.

Please let us know if you need any additional details.

Thanks!
Chakra