The clock nets need to use the same clock routing resource

Question

I’m using AMI/1.8.1 and vitis/2019.2. And I’m using myself dut. When I compile project using vitis, it will prompts “ ERROR: \[Place 30-838] The following clock nets need to use the same clock routing resource”.But when I compile project with same dut using sdx/2018.2, the progress is completed successfully. There is no error.   
    This is the error details “ ERROR: \[Place 30-838] The following clock nets need to use the same clock routing resource, as their clock buffer sources are locked to sites that use the same routing track. One or more loads of these clocks are locked to clock region(s) X1Y13 X2Y13 X2Y14 X3Y13 X3Y14 X4Y13 X4Y14 X5Y13 X5Y14 which causes the clock partitions for these clocks to overlap. This creates unresolvable contention on the clock routing resources. If the clock buffers need to be locked, we recommend users constrain them to a clock region and not to specific BUFGCE/BUFG_GT sites so they can use different routing resources. If clock sources should be locked to specific BUFGCE/BUFG_GT sites that share the same routing resources, make sure loads of such clocks are not constrained to the same region(s). Clock nets sharing routing resources:  
WRAPPER_INST/CL/fec_verify_1/inst/inst_example/inst_example_vadd_m00_axi/inst_axi_dut_bridge/code_loop_0/encoder/enc_out_valid  
WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/clk_out4  
ERROR: \[Place 30-678] Failed to do clock region partitioning: failed to resolve clock partition contention for locked clock sources.”  
    Although the "clk_out4" is a clock, the "enc_out_valid" is not a clock. So it is very confused.  
  
Edited by: zqsteve on Aug 25, 2020 7:30 PM

Answer

I'm not sure that there is generalized Tcl that could be used for any design to find this. Are you able to open the netlist design within Vivado? If so, selecting the clock nets driving into and driving out of the dynamic region would help. The properties tab will show the number of number of loads as the FLAT_PIN_COUNT - 1, as one of the pins that is counted is the driver.  
  
The loads can be added one one of two ways  
-Through source files.  
-Through netlist edits using ECO commands (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug904-vivado-implementation.pdf#page=158)

Answer

Hi,  
  
I had the same problem, perhaps this: https://forums.aws.amazon.com/message.jspa?messageID=944390#944390 can be useful to you as well.  
  
Mikhail

Answer

Adding the answer record with the above suggestions.  
  
https://www.xilinx.com/support/answers/75539.html

Answer

I have soled this problem by inserting bufg for clock in our dut.

Answer

Hi @zqsteve  
  
From the messaging, this should be related to a reported issue that is currently being worked on. The Vivado Error ID is missing, but the rest of the text looks to match. The reported issue was found to have boundary clock(s) between the static and dynamic regions, where there were no loads in the boundary that was crossed. A known workaround is to add loads to a load-less boundary clock.

Answer

How can I tell which clock lacks load? Then how can I add loads to the load-less boundary clock ?

Answer

I have also found that disabling phys_opt_design in the implementation flow can be used as a workaround. I would think this would be easier to test as well.

Answer

To clarify on the suggested workarounds for this issue, three suggestions are available.  
  
1 Try to control the clock tracks usage using properties like CLOCK_LOW_FANOUT if the loads of the one of the clock nets are in the recommended range for CLOCK_LOW_FANOUT.  
2 Disable the post placement's phys_opt_design step in the implementation proces if your WNS at post-placement is reasonably good.  
3 If you are observing the issue only in second implementation in the DFX flow, Keep all these clocks in design in the first implementation itself, so that first implementation in the DFX flow (where the static region is implemented and locked down) is run in the context of all clocks in the design.

The clock nets need to use the same clock routing resource

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