Questions tagged with FPGA Development

# Problem: I started an EC2 instance running the FPGA Developer AMI, and tried to use Vivado to create a new project that wraps custom Verilog Designs for use in Amazon F1 FPGAs. So far, I cannot get Vivado to synthesize anything other than the Demo projects. # Steps: 1. On an EC2 instance running the FPGA Developer AMI: open a terminal, create a directory named "test_fpga", cd into the directory 2. run `source ~/.../aws-fpga/hdk_setup.sh` 3. run `vivado` 4. When Vivado starts, click "Create a new Project". Select all defaults 5. In the Tcl console run: `aws::make_ipi` 6. This creates a block diagram in which the f1_inst block is created and not connected to anything. click "Run Synthesis". Vivado returns an error message saying that it cannot find modules such as Microblaze. **The synthesis fails.** # Conclusion: Is there **any** documentation explaining how to create a new project and synthesize it? I can synthesize the cl_hello_world example by running `aws::make_ipi -examples cl_hello_world` in the Tcl console, but I'm not asking how to customize one of these projects, I'm asking how to start a new Vivado project, add my own Verilog files, and connect those designs to the F1_inst block. Please help, Thanks

# Steps: 1. git clone https://github.com/aws/aws-fpga.git 2. source hdk_setup from the aws_fpga directory 3. create Vivado_init.tcl with line: source $::env(HDK_SHELL_DIR)/hlx/hlx_setup.tcl 4. vivado - This starts Vivado in the remote desktop 4. created the custom command button to run aws::make_ipi. 5. click the custom command button - This creates a new block diagram with the f1_inst block connected to the s_sh input 6. click the run Synthesis button - Synthesis starts and then ends with an error message: - **Could not find module 'bd_1827_mircroblaze_l_0'. The XDC file /home/centos/test_fpga_project/test_fpga_project/sources_1/bd/cl/ip/cl_f1_inst_1/bd_0/ip/ip_0/bd_1827_microblaze_1_0.xdc will not be read for any cell of this module.** # Result: I cannot use Vivado to build any design that uses the F1 FPGAs. # Please Help: Please tell me how I can create a minimal design starting with a **new project**.

Hello, we'd like to run our FPGA machines inside our EKS cluster. Does anyone know of a working AMI/ECR image combination that would allow this to happen? We've tried rolling our own in several ways with no success. Thanks in advance.

Is support for using SDAccel 2018.2 still available i.e. AMI 1.5.x? While creating new instance I can see no earlier than 1.10x!

Looking into getting data retention working for my design and I came across below requirement in the documentation. "The AFI must use all four DDR controllers. (All of DDR_A_PRESENT, DDR_B_PRESENT, DDR_D_PRESENT must be set. DDRC is part of the shell and is always present.)" My design only uses DDRC so I only care about DDRC data retention. Can I get away with not instantiating the other three DDR controllers or they're necessary for some reason?

Tried to spin up an F1 instance in the NoVA data center yesterday and was unable to for at least 15 minutes after which I gave up. Haven't had this happen before and was curious as to the reason and if there are any statistics about availability as this potentially impacts my realtime service. Error message reads like all instances were utilized. And I wanted to confirm this can't happen with reserved instances? And is there an easy way to be agnostic to data center to minimize this risk for on demand instances? AWS CLI returned message "An error occurred (InsufficientInstanceCapacity) when calling the StartInstances operation (reached max retries: 4): Insufficient capacity."

I am trying to use the cl_ila same as in cl_dram_dma., i.e, I have the 2 AXI busses to monitor using ILA. However the synthesis script cannot seem to find the cl_debug_bridge module. Which files/options etc need to be modified in build/scripts to synthesise the ILA?

Hey everyone, I've recently bumped to a newer AMI which brings in Vivado 2020.2, I was previously on 2018.4. I've noticed that Vivado has gotten much more strict about hiding the names of cells in reports and checkpoints. This makes timing reports for designs that fail to meet timing unusable as debugging tools. Since we can't afford to rerun the flow on timing failures, to work around this i've removed the calls that encrypt sources in encrypt.tcl. The uploaded DCP is still encrypted, so AGFI generation seems to work OK. Given this, why is it suggested that we encrypt RTL sources? Does this change if we are not sharing AGFIs outside of our institution?

Locally done by instantiating an MMCM and then accessing its PSEN, PSINCDEC, PSCLK and PSDONE ports. I'm just getting started but couldn't find a concrete answer to this, sorry if it's a dumb question. Thanks!

Hi. I am using FPGA Developer AMI 1.11.0 and was running hello_world example from https://github.com/aws/aws-fpga/blob/master/Vitis/README.md, using "make all TARGET=hw DEVICE=$AWS_PLATFORM" I am using m5.xlarge on us-west-1. Unlike the run using previous AMI version, it no longer progresses after the point: ============================== \[11:44:52] Run vpl: Step create_project: Completed \[11:44:52] Run vpl: Step create_bd: Started \[11:45:23] Run vpl: Step create_bd: Completed \[11:45:23] Run vpl: Step update_bd: Started \[11:45:23] Run vpl: Step update_bd: Completed \[11:45:23] Run vpl: Step generate_target: Started \[11:46:36] Run vpl: Step generate_target: Completed \[11:46:36] Run vpl: Step config_hw_runs: Started \[11:46:41] Run vpl: Step config_hw_runs: Completed \[11:46:41] Run vpl: Step synth: Started ============================== When I type "top" - vivado CPU utilization goes down to near 1%. (not killed - just not working) So I looked at "./_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/vivado.log", and it has ended at the point ============================== \[Mon Sep 6 11:46:44 2021] Launched my_rm_synth_1... Run output will be captured here: /home/ec2-user/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/hello_world/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/my_rm_synth_1/runme.log \[Mon Sep 6 11:46:44 2021] Waiting for my_rm_synth_1 to finish... ============================== From comparing with logs with previous version, I think Vivado should get launched at this point to do synthesis, but it is not happening. I know it is a vague description of the problem, but is there some commands I can try to figure why it has stopped working? I suppose Vivado program is waiting for some routines to finish, and they are not responding back - but not sure what to check. Thanks.

Hi All, Based on the output of lsmod command and documents (https://github.com/aws/aws-fpga/blob/master/sdk/linux_kernel_drivers/xdma/xdma_install.md ), the default driver for CentOS is xocl. But I did not find xocl in lsmod output on Amazon Linux 2, what is the default driver for Amazon Linux 2? And can we install xdma for both operating systems? Thanks! Best, Sam Edited by: SamTian on Aug 23, 2021 10:10 PM Edited by: SamTian on Aug 23, 2021 10:11 PM

Seeing a intra-clock timing violation between clocks "rdck" and "tck" (both associated by dbg_hub) after enabling DDRA and connecting a CDMA IP to it. Notes: 1) dbg_hub is automatically added by vivado. 2) Getting Critical Warnings when vivado processes file "cl_debug_bridge_hlx.xdc" 3) Added false clock path between drck and tck to "cl_synth_user.xdc" has no effect. 4) Using Vivado 2020.1 and Shell shell_v04261818 I realize that by adding DDRA, I am adding debug that comes with the DDR PHY so my guess is there is an issue with the constraints in file "cl_debug_bridge_hlx.xdc"??? Has anyone ever run into this ? Thanks Brian

Hi, I referred to Multiple devices example project and updated my project to work with multiple fpga devices <https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.2/sys_opt/multiple_devices>. I am successful with using the f1.4xlarge instance and I am able to get the expected results. However, when I try to run inference on f1.16xlarge, it throws the following error: _terminate called after throwing an instance of 'xrt_xocl::error'_ _what(): No devices found_ _Aborted_ I tried setting the XCL_EMULATION_MODE=hw, unset XCL_EMULATION_MODE and set up the environment using _source $AWS_FPGA_REPO_DIR/vitis_runtime_setup.sh_ It appears that the line in host code which corresponds to this error is _auto devices = xcl::get_xil_devices();_ Note: the xcl2.cpp and xcl2.hpp are in ./libs folder. Kindly suggest on what I can try to resolve this problem. Thanks

Hello all, I'm interested to hear if AWS is willing to share their plans on future version of OS that will be used for FPGA AMI. Currently, FPGA AMI is running on CentOS 7 (or Amazon Linux 2, which is based on CentOS), which is already pretty ancient, and will see end-of-support in 2024. Also, RHEL has announced that CentOS releases will stop in currently known form, and they'll start with "rolling releases". This all leads me to believe that AWS will, at some point, stop using CentOS 7, and switch to either rolling release CentOS, or perhaps some other Linux distro. By reading the documentation and this forum, I've concluded that using Ubuntu with Vivado is currently not supported on AWS Instances, but Ubuntu is able to handle AWS PCIe drivers, meaning that FPGA designs synthesized on CentOS 7 are available to be used on Ubuntu. Is this still valid statement?

Hello, I was unable to locate the documentation for configuration registers in the shell which XDMA driver uses to control DMA operation. Can you please provide the pointer? Thanks

Working my way through the walkthrough on this page: - https://github.com/aws/aws-fpga/blob/master/Vitis/README.md Upon performing these steps: $ cd $VITIS_DIR/examples/xilinx/hello_world $ make clean $ make run TARGET=sw_emu DEVICE=$AWS_PLATFORM all The last step gets me this error: utils.mk:45: *** XILINX_XRT variable is not set, please set correctly and rerun. Stop I see some mention of XILINX_XRT when I searched these forums, but not this exact error message, so thought I'd post here for any clues on what to do :)

I was trying to follow steps here: https://github.com/aws/aws-fpga/blob/master/Vitis/docs/Setup_AWS_CLI_and_S3_Bucket.md But this suggested step failed for me: $ aws s3 mb s3://<bucket-name>/<dcp-folder-name> # Create folder for your tarball files Prior to this, I had done this step successfully: aws s3 mb s3://gurce-fpga-afi But then I tried the next-suggested line, with: aws s3 mb s3://gurce-fpga-afi/dcp-tar make_bucket failed: s3://gurce-fpga-afi/dcp-tar An error occurred (BucketAlreadyOwnedByYou) when calling the CreateBucket operation: Your previous request to create the named bucket succeeded and you already own it. I'm starting to suspect that the 'aws s3 mb' command is just for making a bucket, and not for creating a folder. From what I've learnt about s3 buckets so far, the folder is more of an abstraction that doesn't genuinely exist. So perhaps I should skip this step and do the steps below it? (And that will implicitly create such a folder?) $ touch FILES_GO_HERE.txt # Create a temp file $ aws s3 cp FILES_GO_HERE.txt s3://<bucket-name>/<dcp-folder-name>/ # Which creates the folder on S3 Ok, I tried this, and yep, it seemed to work: aws s3 cp FILES_GO_HERE.txt s3://gurce-fpga-afi/dcp-tar/ ...but still, it seems odd to have that failing step in the instructions, should it be removed?

Hi, I am using AWS F1 for FPGA development from an year I had this basic question from long time. Right now I have selcted a0 clock recipe for my design which is main clock. As per my understanding clock frequency should depend on critical path in design and may change from design to design or is it like in AWS environment if it will see that for given clock recipe if it finds critical path then it will throw an error in synthesis? We can choose any clock frequency a0 or a1 for CL design ? Another question I had , I am running all my design in non gui mode and have extended from hello world design. After running simulation or synthesis if I want to open project in gui mode what are the steps to do it ? Is there any documentation available for the same ?

I'd like to calculate the peak bandwidth available to custom logic using the AWS F1 DDR interface. Tutorial video 2 has the following statements about DDR: * 4 DDR channels each having 16Gb, 72-bit wide of ECC memory * 4 DDR channels, each 12 Gbit/sec * 2400 MT/sec @1.2 GHz @ 72-bits * maximum bandwidth of 48 Gbit/sec * 512-bit busses at 250 MHz * max bandwidth of 16 Gbit/sec Some questions: 1. Some of these statements conflict with each other? For instance, each 512-bit data interface at 250 MHz = 512-bits * 0.25 G/sec = 128 Gbit/sec but the max bandwidth is stated at 16 Gbits/sec. 2. How many outstanding reads/writes can be supported at a time per DDR interface - is it 16? 3. What is the approximate latency of a DDR read/write relative to the 250 MHz clock? 4. Does the DDR memory controller serialize a 512-bit read request at 250MHz clock into 8 x 64-bit requests to the DDR 1.2 GHz or 1.4 GHz memory and present the data back to the CL logic as a 512-bit access? Thanks for your help. Azimuth Technology

Hello, I am using Vitis flow to create an RTL kernel. I have an intentional 'combinatorial loop': In the design, multiplexers are used to connect some number of LUTS in different ways based on a register value. Register value will never be such, that LUTS are connected in an actual loop, but the synthesis tool still sees it as one. Is there a way to write a constraint to break the loop during Timing analysis, like when working with the Vivado on a local board. If there is none, and loops are generally prohibited, do you know if it is noted in any documentation, so I can deliver that as a formal confirmation? Thanks in advance, Djordje

I am creating a 3 D signal as shown below and I understand that this would be implemented as register. **"logic \\[N-1:0\]\\[N-1:0\]\\[1:0\] X;"** But When I run synthesis with N=64 it works perfectly while for N=128, synthesis is stuck at warning as shown below. Is it too much large number of registers to run on vertex ultrascale plus FPGA ? **"WARNING: \\[Synth 8-5856\] 3D RAM X_reg_reg for this pattern/configuration is not supported. This will most likely be implemented in registers"** How can I know numbers of block RAM instances and their characteristics (such as maximum width etc) is supported by particular F1 instance ? Edited by: aiquanta on Jul 18, 2021 4:49 AM Edited by: aiquanta on Jul 18, 2021 4:49 AM Edited by: aiquanta on Jul 18, 2021 4:50 AM Edited by: aiquanta on Jul 18, 2021 4:51 AM Edited by: aiquanta on Jul 18, 2021 4:51 AM

Hi, How can we add a wire (or some wires) to connect an HLS kernel and an RTL kernel in Vitis? I want to use the RTL kernel to read some values in the HLS kernel for debugging. Can we avoid using the "Streaming Connection" which is too much for the simple reads? Thank you! Sam

Hi. This is a follow-up to post https://forums.aws.amazon.com/thread.jspa?messageID=990108&#990108. I successfully installed NICE DCV for FPGA development using the guide (https://github.com/aws/aws-fpga/blob/master/developer_resources/DCV.md), and was able to launch vitis_hls (GUI) in my web browser. The problem is that vitis_hls crashes very often (about every 10 minutes), with the error message on the upper right corner: "A Problem has Occurred A problem in the gnome-terminal-3.28.2-3.el7 package has been det..." and this error message goes away about 5 seconds later. (I am not sure how to view more detailed message...) I first thought it was due to lack of memory in m5.xlarge, so I switched to m5.2xlarge, but the problem persists. I also checked the problem exists in both N. California and Seoul AWS server as well. I also did some quick search on AWS Forum - nothing comes up. Could anyone help me with this?

Hi. This is a follow-up question to: https://forums.aws.amazon.com/message.jspa?messageID=990108#990108 I am using Vitis HLS GUI on AWS M5.xlarge instance with FPGA Developer AMI 1.10.0 I am currently in Los Angeles and logging into N. California AWS server, so latency shouldn't be too bad. I create a simple project with source files which I know synthesized correctly in my own servers with Vitis HLS 2020.2. But when I pressed "Synthesis" (the green arrow button) or when I pressed CSim (in the pull-down menu), Vitis HLS simply hangs and does not respond. No error message - simply hangs. The program itself is not dead - it does accept other commands, such as switching to Debug tab. Could anyone help me solve this problem?

Hi. I was trying to launch Vitis HLS GUI with FPGA Deveoper AMI 1.10.0. I did "git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR", and then "cd $AWS_FPGA_REPO_DIR" and then "source vitis_setup.sh" and then "source /opt/Xilinx/Vitis_HLS/2020.2/settings64.sh" but when I launch "vitis_hls", I get message: ================================= ****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source /opt/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace INFO: \[HLS 200-10] Running '/opt/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls' INFO: \[HLS 200-10] For user 'centos' on host 'ip-xxx-xx-xx-xx.ap-northeast-2.compute.internal' (Linux_x86_64 version 3.10.0-1160.6.1.el7.x86_64) on Tue Jul 13 06:47:43 UTC 2021 INFO: \[HLS 200-10] On os "CentOS Linux release 7.9.2009 (Core)" INFO: \[HLS 200-10] In directory '/home/centos' INFO: \[HLS 200-10] Bringing up Vitis HLS GUI ... INFO: \[Common 17-206] Exiting vitis_hls at Tue Jul 13 06:47:48 2021... ============================================== So, pretty much no information on why it is not launching. I can launch xeyes, so I don't think it is X problem. If there additional dependencies I should install for Vitis HLS GUI, could anyone tell me the list?

Hi, I am looking for information explaining how to access DDR memory from host, but NOT from logic contained in the CL. Here is the background: Using 2 FPGA instance, I was able to do send data from 1st FPGA pciemaster to the 2nd FGPA ddr. Now I want to read the 2nd FPGA DDR data and do data compare, not hardware compare as implemented in cl_tst module. Please advice on to achieve this. Regards, Venkat

Hey guys, I was wondering about the provenance of these three constraints that appear in some but not all of the example designs. Under what circumstances are they required? In my designs, now based off cl_dram_dma, (which has them commented out)<https://github.com/aws/aws-fpga/blob/v1.4.20/hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc#L64>), only the latter two correctly resolve. set_clock_groups -name TIG_SRAI_1 -asynchronous -group \\[get_clocks -of_objects \\[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O\]\] -group \\[get_clocks -of_objects \\[get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0\]\] set_clock_groups -name TIG_SRAI_2 -asynchronous -group \\[get_clocks -of_objects \\[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O\]\] -group \\[get_clocks drck\] set_clock_groups -name TIG_SRAI_3 -asynchronous -group \\[get_clocks -of_objects \\[get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O\]\] -group \\[get_clocks -of_objects \\[get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O\]\] Can i safely remove all three?

Hi there, I was having a play with the AMI just now, and I was thinking to see if I could build something for the older Artix 7 series parts (xc7a100tcsg324-3). But I'm getting the impression that only the UltraScale series parts are available. I thought I'd try and run Vivado and go to "Help >> Add Design Tools or Devices...", but this got me an error of: Cannot run program "/opt/Xilinx/.xinstall/Vivado_2020.2/xsetup": error=2, No such file or directory (and indeed, there is no "/opt/Xilinx/.xinstall/" folder in the instance, I guess it was deleted?) Anyways, just wondered if you had any ideas. At a guess, perhaps making use of this AMI was tailored specifically for the F1/UltraScale hardware, and perhaps if I need other devices, I'd need to prepare my own AMI with those other series-7 parts installed too?

I am following the HDK getting started guide, in particular I am trying to execute the " <https://github.com/aws/aws-fpga/blob/master/hdk/README.md#how-to-create-an-amazon-fpga-image-afi-from-one-of-the-cl-examples-step-by-step-guide>" for the hello world example. I have successfully executed the first part - building the custom logic and publishing my new AFI. I have obtained the AFI ID and the AGFI ID. I have confirmed by executing `aws ec2 describe-fpga-images ` my AFI is available and I have verified it is in the bucket. The second part of the guide is about "how to load and test a registered AFI from withing an F1 instance". I have created an f1.2xlarge instance using the Centos FPGA Developer AMI. The welcome message is > login as: centos > Authenticating with public key "imported-openssh-key" > Last login: Thu Feb 25 15:40:14 2021 from 72-21-196-65.amazon.com > ___ ___ ___ _ ___ _____ __ _ __ __ ___ > | __| _ \/ __| /_\ | \| __\ \ / / /_\ | \/ |_ _| > | _|| _/ (_ |/ _ \ | |) | _| \ V / / _ \| |\/| || | > |_| |_| \___/_/ \_\ |___/|___| \_/ /_/ \_\_| |_|___| > AMI Version: 1.10.0 > Xilinx Version: 2020.2 > Readme: /home/centos/src/README.md > AMI Release Notes: /home/centos/src/RELEASE_NOTES.md > GUI/Cluster setup: https://github.com/aws/aws-fpga/blob/master/developer_resources > Developer Support: https://github.com/aws/aws-fpga/blob/master/README.md#developer- support > Centos Common code: /srv/git/centos-git-common > Xilinx XRT source: https://github.com/Xilinx/XRT Now, the instructions read: > git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR > cd $AWS_FPGA_REPO_DIR > source sdk_setup.sh (small aside: it would be best IMHO to provide the snipped with the definition of `$AWS_FPGA_REPO_DIR` again; the wording instructs to launch a new VM so I think definition cannot be assumed). So far everything look ok. I also ran `aws configure` as instructed. OK. Next step would be `sudo fpga-clear-local-image -S 0` This is what happens in reality: > \[centos@fpgadevc aws-fpga] sudo fpga-clear-local-image -S 0 > sudo: fpga-clear-local-image: command not found Related FPGA commands don't seem to work either. I don't really know where to find them but I was more focused in going by the book for now. I have tried to understand why those commands don't work and I am so far out of clues. What did I miss? Edited by: MaxDZ8 on Jul 4, 2021 9:02 AM - fix some layout Edited by: fixed more formatting woes.

Hi, I have a design which split into two modules and I need to load each module into seperage FPGAs. (in this case 2 FPGA's). Without AWS, I would have used two FPGA boards each loaded with a respective image and both are connected/routed through the FMC connecter. How to achieve the same using AWS F1.4xlarge (which has two FPGA's in one group)? Regards, Venkat

Hi, I am new to AWS FPGA Development. My task is, Using f1.x4large instance, I need to transfer packetized data from one FPGA to another FPGA. After power-on, by design one FPGA is defined as Sender and the other as Receiver. And Sender starts sending packets one at a time and the gap between the two packets is huge. On receiving the correct packet, the receiver acknowledges this with an ACK packet. Both Sender and Receivers maintain transmit and receive packet counters. This data transfer happens without driver involvement. The driver should be able to access the transmit and receive count register and other registers. I have gone through the example DMA test cases. I couldn't understand how to communicate without any driver involvement. Appreciate your help. Regards, Venkat

Hi, I am new to AWS FPGA Development. My task is, Using f1.x4large instance, I need to transfer packetized data from one FPGA to another FPGA. After power-on, by design one FPGA is defined as Sender and the other as Receiver. And Sender starts sending packets one at a time and the gap between the two packets is huge. On receiving the correct packet, the receiver acknowledges this with an ACK packet. Both Sender and Receivers maintain transmit and receive packet counters. This data transfer happens without driver involvement. The driver should be able to access the transmit and receive count register and other registers. I have gone through the example DMA test cases. I couldn't understand how to communicate without any driver involvement. Appreciate your help. Regards, Venkat

I'm using 1.4.8 still while we're working to upgrade in https://forums.aws.amazon.com/thread.jspa?threadID=338653. My understanding is that URAMs are not initialized to 0 when the AGFI is loaded onto the f1 host. Because of that, I need to avoid using them unless I explicitly instantiate them because extra inferred instances may violate some assumptions we currently have. We do use some URAMs explicitly in the design and I see that a few are used in the shell as well. Does passing '-max_uram 0' to synth_design when synthesizing the CL only disable inference of URAMs or will it cause an error if we explicitly instantiate the primatives in places? Does `fpga-clear-local-image` then `fpga-load-local-image` clears the URAMs into a known state? It's possible that my understanding of the URAM initial state mentioned earlier is incorrect. Edited by: TimSnyder on May 18, 2021 7:31 AM Edited by: TimSnyder on May 18, 2021 1:37 PM

Hello all, I've built a design where I planned to test XDMA functionality, as well as Peek/Poke functionality. Here is the image of the design: https://imgur.com/Mx4HVDq Address map: https://imgur.com/Bmg87S6 F1 IP settings: https://imgur.com/G5WPoFH AFI: afi-0a8ee3b4101930666, AGFI: agfi-08d6f213d9161b558 dmesg log after fpga-load-local-image {AGFI} call: https://pastebin.com/L3eRq5Nd Here is the code and output I tried to use for testing XDMA. https://pastebin.com/XVnpVZA6 Here is the code and output I tried to use for testing Peek/Poke https://pastebin.com/T8eRQEhS None of these two produce any dmesg output. Few questions: 1. Any reason why I'm not successful in read/write over XDMA to BRAM (DDR operations are successful)? 2. Why is Peek/Poke failing? 2. Should I be able to use Peek/Poke over PCIS interface (not in the same time when using PCIS for XDMA), or should I use OCL instead? EDIT: To correct myself, I shouldn't even be able to write to BRAM via XDMA on this design, but I observed that on a design that is same like this one, just without OCL enabled. EDIT 2: I discovered that I need SUDO to be able to attach execute fpga_pci_attach. Is there any way to work around that, and not use SUDO? Anyway, now peek/poke is functional. Still, question of writing to BRAM element via XDMA persists. Edited by: jelicicm on May 18, 2021 6:48 AM

Hey guys, I want to add DDR to my FPGA project and as a first step I'm trying to run the CL_DRAM_DMA "test_dram_dma_hwsw_cosim" simulation example with C++ instead of C compiler. First I had the problem that init_ddr() was not defined but after I added C++ guards in the 'sh_dpi_tasks.h' file around the function declarations, the DDR initialization went through. However, now I get an error for the sv_fpga_start_buffer_to_cl() function, see below: ... Done DDR init... filling buffer with random data... Now performing the DMA transactions... FATAL_ERROR: Vivado Simulator kernel has encounted an exception from DPI C function: test_main(). Please correct. Time: 40592 ns Iteration: 0 Process: /tb/sv_fpga_start_buffer_to_cl File: /home/centos/src/project_data/aws-fpga/hdk/common/verif/include/sh_dpi_tasks.svh ... Do you have any advice for what I have to change to make this work? I'm relatively new to the platform... Thanks! ******* Has been resolved. There was a memory allocation error... Edited by: kaja1992 on May 6, 2021 7:23 PM

Hi I am getting an error when I try create an AFI with a 2020.2 Vitis .xclbin. I'm using aws-fpga v1.4.19. It seems like Vivado 2020.1 is being used. #----------------------------------------------------------- # Vivado v2020.1 (64-bit) # SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # Start of session at: Sat Apr 10 14:48:42 2021 # Process ID: 11292 # Current directory: /home/builder/scripts # Command line: vivado -mode batch -source ingest.tcl # Log file: /home/builder/scripts/vivado.log # Journal file: /home/builder/scripts/vivado.jou #----------------------------------------------------------- source ingest.tcl # set userDCP "../checkpoints/SH_CL_routed.dcp" # set awsDCP "../checkpoints/SH_CL_BB_routed.dcp" # set awsDCPStripped "../checkpoints/SH_CL_BB_stripped.dcp" # set powerDefaultRPT "../reports/power_report.default.rpt" # set powerStaticRPT "../reports/power_report.static.rpt" # set timingRPT "../reports/SH_CL_final_timing_summary.rpt" # set ioRPT "../reports/report_io.rpt" # set partialBIT "../bitstreams/SH_CL_final_pblock_CL_partial.bit" # set partialLTX "../bitstreams/SH_CL_final_pblock_CL_partial.ltx" # set CL_PATH WRAPPER_INST/CL # puts "Ingest start time: \\[\[clock format \[clock seconds\] -format {%a %b %d %H:%M:%S %Y}\]\]" Ingest start time: \[Sat Apr 10 14:51:01 2021\] # set_param hd.supportClockNetCrossDiffReconfigurablePartitions 1 # set_param hd.platformVerifyCachedRun false # check_integrity $userDCP INFO: \[Vivado 12-5531\] Integrity check successful: /home/builder/checkpoints/SH_CL_routed.dcp check_integrity: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2181.945 ; gain = 0.004 ; free physical = 66549 ; free virtual = 89717 # set_msg_config -severity INFO -suppress # set_msg_config -severity STATUS -suppress # set_msg_config -severity WARNING -suppress CRITICAL WARNING: \[Common 17-1355\] You are suppressing all messages of type 'WARNING'. You may potentially disregard important DRC, CDC, and implementation messages that can negatively impact your design. If this is not desired, please run 'reset_msg_config -suppress -severity {WARNING}' to undo this change. # set_msg_config -id {Chipscope 16-3} -suppress # set_msg_config -string {AXI_QUAD_SPI} -suppress # puts "Opening user DCP $userDCP: \\[\[clock format \[clock seconds\] -format {%a %b %d %H:%M:%S %Y}\]\]" Opening user DCP ../checkpoints/SH_CL_routed.dcp: \[Sat Apr 10 14:51:09 2021\] # open_checkpoint $userDCP ERROR: \[Runs 36-378\] The checkpoint '/home/builder/checkpoints/SH_CL_routed.dcp' was created with 'Vivado v2020.2 (64-bit)', and cannot be opened in this version. Edited by: Yaniv42 on Apr 10, 2021 8:51 AM

Hi everyone! I am trying to build XRT for Xilinx SDX 2018.2 and using Xilinx community AMI or AWS FPGA AMI v1.5.1. I am having problem with installing devtoolset 6. I have tried some workarounds such as changing repo, etc. Yet, it still cannot install it. I also cannot build with devtoolset 7 8. What am I missing to configure? Thanks a lot! Edited by: yonselyuksel on Mar 13, 2021 4:03 PM Edited by: yonselyuksel on Mar 14, 2021 8:01 AM

I’m working on optimizing my project, which uses DMA, and have a few questions about best practices on the software side of things as I’m more of an RTL person. My design is a search engine that compares data provided to the FPGA from the computer against a reference library stored in the DDR. I load GBs of data to the DDR in a single dump on startup but then need to make ~100 4kB writes per second to keep the library updated. The data in each update is written to consecutive DDR addresses but the updates are scattered throughout the DDR address space. My drivers use fpga_dma.h. Questions: 1) Is it better practice to open a DMA queue a single time and store the descriptor in my driver library, which would potentially leave the queue open for days, or should I open and close the DMA queue every time I do a write? 2) I’d like to have the XDMA driver load automatically when the F1 instance is powered up but it’s not doing that after I follow the instructions in the link below. Is it supposed to be persistent? I’m using the FPGA Dev AMI v1.9.1 but am having to follow the full instructions each time so DMA works, maybe because of the XOCL driver conflict as it seems to be coming back each reboot. Very possible I've screwed up something as my unix skills are google/cut/paste. https://github.com/aws/aws-fpga/blob/master/sdk/linux_kernel_drivers/xdma/xdma_install.md#xdmainstallfail

I am using aws_build_dcp_from_cl.sh script to run synthesis and once synthesis is complete tar file is generated from which I can generate afi. When I run synthesis in vivado gui I can see implementation schematic. How I can do the same when running synthesis in bach mode ? Edited by: aiquanta on Mar 7, 2021 1:32 PM

We have two xpfm setup (basically two different versions of the F1 shell) and we have generated bitfiles with them. The name of these two xpfm files are: * xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm *xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xpfm I believe the latter is the one which works with Vitis 2019.2 and later versions. When we program either of the bitfiles on an F1.2xlarge instance with AMI 1.7.1 (FPGA Developer AMI - 1.7.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-073c0053d4be15233.4 - ami-0c9c61319a32e0692) it passes. But when we program either of the bitfiles on F1.2xlarge instance with AMI 1.8.1 (FPGA Developer AMI - 1.8.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0c90eb898f6c9f1bd.4 - ami-0209388abb64ef69c) or AMI 1.9.1 (FPGA Developer AMI - 1.9.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0c3a51e8e73a7fa94.4 - ami-03d255ca72d04ce3e) they fail with the following error messages: **root@ip-172-31-4-120 ~# awssak program -p /tmp/binary_container_1_dynamic.awsxclbin** **xclProbe found 1 FPGA slots with xocl driver running** **INFO: Found 1 device(s)** **IOCTL DRM_IOCTL_XOCL_READ_AXLF Failed: -1** **ERROR: awssak program failed.** For newer version bitfile, dmesg shows the following errors: **\[Sat Feb 20 00:47:28 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: did not find platform dtb** **\[Sat Feb 20 00:47:28 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: Failed to download xclbin, err: -22** and for the older version bitfile, dmesg shows the following error: **\[Sat Feb 20 00:47:18 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: Failed to download xclbin, err: -110** Can you please guide us why this is happening? Edited by: shahrzad on Mar 3, 2021 11:52 AM

Hi there, Once I try to load my local image, I obtain the following error: $ sudo fpga-load-local-image -S 0 -I agfi-0c5a45f4871941614 Error: (12) cl-id-mismatch The vendor and device ID presented by the CL did not match expected values provided at ingestion time. The clear request runs successfully before loading. $ sudo fpga-clear-local-image -S 0 AFI 0 none cleared 1 ok 0 0x04261818 AFIDEVICE 0 0x1d0f 0x1042 0000:00:1d.0 Describe request after failed load attempt is the following: $ sudo fpga-describe-local-image -S 0 -H Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion AFI 0 none load-failed 7 cl-id-mismatch 12 0x04261818 Type FpgaImageSlot VendorId DeviceId DBDF AFIDEVICE 0 0x1d0f 0x1042 0000:00:1d.0 What am I missing here? How can I resolve this issue?

Hi there, Once I try to load my local image, I obtain the following error: $ sudo fpga-load-local-image -S 0 -I agfi-0c5a45f4871941614 Error: (12) cl-id-mismatch The vendor and device ID presented by the CL did not match expected values provided at ingestion time. The clear request runs successfully before loading. $ sudo fpga-clear-local-image -S 0 AFI 0 none cleared 1 ok 0 0x04261818 AFIDEVICE 0 0x1d0f 0x1042 0000:00:1d.0 Describe request after failed load attempt is the following: $ sudo fpga-describe-local-image -S 0 -H Type FpgaImageSlot FpgaImageId StatusName StatusCode ErrorName ErrorCode ShVersion AFI 0 none load-failed 7 cl-id-mismatch 12 0x04261818 Type FpgaImageSlot VendorId DeviceId DBDF AFIDEVICE 0 0x1d0f 0x1042 0000:00:1d.0 What am I missing here? How can I resolve this issue?

Hi, Is there ant common solution for a bridge from APB in Xilinx IP lib ( or other simple parallels bus) to AXI 4? I am asking it because I need to implement bridge from the APB bus to the DDR Controller's AXI 4 interface. Regards Gil

I’m using AMI/1.8.1 and vitis/2019.2. And I’m using myself dut. Now I’m using aurora_64b66b. I want to use k code(K28.5). Where to view the K code(K28.5) for Aurora64B66B?

Hey, I'm connecting to my F1 instance using SSH when trying to start vivado I get: ***** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. start_gui Exception in thread "main" java.lang.UnsatisfiedLinkError: /opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib/libawt_xawt.so: libXtst.so.6: cannot open shared object file: No such file or directory at java.base/java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.base/java.lang.ClassLoader.loadLibrary0(Unknown Source) at java.base/java.lang.ClassLoader.loadLibrary(Unknown Source) at java.base/java.lang.Runtime.load0(Unknown Source) at java.base/java.lang.System.load(Unknown Source) at java.base/java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.base/java.lang.ClassLoader.loadLibrary0(Unknown Source) at java.base/java.lang.ClassLoader.loadLibrary(Unknown Source) at java.base/java.lang.Runtime.loadLibrary0(Unknown Source) at java.base/java.lang.System.loadLibrary(Unknown Source) at java.desktop/java.awt.Toolkit$3.run(Unknown Source) at java.desktop/java.awt.Toolkit$3.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/java.awt.Toolkit.loadLibraries(Unknown Source) at java.desktop/java.awt.Toolkit.<clinit>(Unknown Source) at java.desktop/sun.awt.AppContext$2.run(Unknown Source) at java.desktop/sun.awt.AppContext$2.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/sun.awt.AppContext.initMainAppContext(Unknown Source) at java.desktop/sun.awt.AppContext.access$400(Unknown Source) at java.desktop/sun.awt.AppContext$3.run(Unknown Source) at java.desktop/sun.awt.AppContext$3.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/sun.awt.AppContext.getAppContext(Unknown Source) at java.desktop/javax.swing.SwingUtilities.appContextGet(Unknown Source) at java.desktop/javax.swing.UIManager.getLAFState(Unknown Source) at java.desktop/javax.swing.UIManager.maybeInitialize(Unknown Source) at java.desktop/javax.swing.UIManager.getDefaults(Unknown Source) at java.desktop/javax.swing.UIManager.put(Unknown Source) at ui.PlanAhead.<clinit>(SourceFile:169) ERROR: \[Common 17-70] Application Exception: JVM: Can't find class: ui/PlanAhead ERROR: \[Common 17-211] Error loading jvm. is there a way to fix that? Thanks

Hello! I'm trying to run a few examples with the Vitis sparse library (https://github.com/Xilinx/Vitis_Libraries/tree/master/sparse). Specifically, I'm trying to run the matrix vector multiplication module in the L2 library. I am wondering if the sparse library is currently compatible with the AWS platform? The reason I ask is that seems like the Makefile here (https://github.com/Xilinx/Vitis_Libraries/tree/master/sparse/L2/tests/cscmv) has some checks on the target platform. Thank you! Owenoool

Hello, The build strategy used in the flow should be mentioned in the manifest sent to AFI generation. currently there are 5 strategies (DEFAULT/BASIC/EXPLORE/TIMING/CONGESTION). Is the developer allowed to use a custom strategy (or – a custom set of steps and options/primitives per each vivado step), or is it a must to use explicitly one of the AWS-provided strategies that have been described above? Thanks,

Hi I am trying to build the DMA-based HDK example (cl_dram_dma) on the FPGA Developer AMI on an EC2 instance. After several hours I hit the following (as recorded in my nohup.out file): \[centos@ip-172-30-0-87 scripts]$ ./aws_build_dcp_from_cl.sh -notify <time passes> \[centos@ip-172-30-0-87 scripts]$ cat 20_08_18-135551.nohup.out <snip> INFO: \[Timing 38-480] Writing timing data to binary archive. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:01:10 ; elapsed = 00:00:28 . Memory (MB): peak = 10315.801 ; gain = 0.000 ; free physical = 15062 ; free virtual = 41662 src/tcmalloc.cc:283] Attempt to free invalid pointer 0x7f32bb3a8000 Abnormal program termination (6) Please check '/home/centos/src/project_data/aws-fpga/hdk/cl/examples/cl_dram_dma/build/scripts/hs_err_pid112936.log' for details \[centos@ip-172-30-0-87 scripts]$ cat hs_err_pid112936.log \[centos@ip-172-30-0-87 scripts]$ Is this a known issue and are there any thing(s) I should be doing in order to prevent it from happening? Stephen

Hi There I am looking for the next level of detail on how the XDMA registers are mapped into BAR2 of the AppPF in the AWS F1 shell. I know I **could** read the XDMA driver code and try and work it out from there but I was hoping there was documentation for this and I was missing it. Any pointers would be appreciated! I am looking for specific offsets in BAR2 and what XDMA registers they map too. I can then use the XDMA IP user guide to work out exactly what those registers can do. Stephen

Looks like in the dram_dma exmple there are a number of floor planning directives to improve timing/routability. I currently do not use DRAM or the DMA in my cl, should I include these constraints in my cl since these interfaces cannot be eliminated from the shell 9but only tied off)? is there more documentation on what these constraints are doing and how they were derived?

Hey all, The AWS F1 documentation mentions that the command "fpga-describe-local-image -S 0 -M" can report power consumed by an AFI. However I could not tell from the documentation if the power consumption that is reported includes power consumed by the DRAM device memory, or if that needs to be measured separately. If the DRAM connected to the FPGA (the device memory) does need to have its power consumption measured separately how do we do that? Thanks!

I’m using AMI/1.8.1. And I use vu9p and vitis to generate the xclbin file. When I used host CPP and AFI, I reported an error while executing host cpp. It prompt：“\[XRT] ERROR: No devices found. Error: Failed to find an OpenCL platform! Test failed”. But I have source /opt/xilinx/xrt/setup.sh before executing host cp. Then , When I use “xbutil dmatest” according ug1393, it prompt: ”INFO: Found total 1 cards, 0 are usable” “ERROR: Card index 0 is out of range. ” So the device or driver have error? I need to terminate the instance, then reinstall the AMI?

Hi, I am using on-prem setup for generating DCP checkpoints in HDK flow for multiple projects. So far, after updating the encrypt.tcl and other relevant files in build/scripts folder, I was able to generate checkpoints. But, with a recent project of mine, I am facing error, where AWS is saying there is nothing to encrypt. Below is the output where it throws error. ``` ## encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile_2017_4.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc] ERROR: [Vivado 12-3330] encrypt 1735: Failed to encrypt ''./home/user/.Xilinx/.temp3fabed45-9f07-491c-89e9-867452be593b/vivado_keyfile_2017_4.txt: FileStructure::encrypt1735: Nothing to encrypt. ``` I have checked the hierarchy of the design, and also created the project from scratch multiple times, but this error stays same. Any pointers on what could be the issue would be really helpful. Thanks in advance.

I see that BAR4 (used by PCIS) is prefetchable per this document: https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Fpga_Pcie_Memory_Map.md How can I disable prefetching for that BAR, similar to BAR0 and BAR1? I know prefetch is a FPGA DMA core setting - but I think it can be disabled in software? I am looking into if/how it could be done in XDMA. I am about to try setting MAX_EXTRA_ADJ=0 (no extra adjacent descriptors to prefetch). https://github.com/aws/aws-fpga/blob/7f1e76765766f579d3a767bedf669019d50342f3/sdk/linux_kernel_drivers/xdma/libxdma.h Any information would be helpful. **Update** Apparently for 64b address space BARs (like BAR4) you cannot disable prefetching? Only for 32b address spaces? Thanks Edited by: absurdfatalism on Jul 5, 2020 7:26 PM

I'm learning to use the Vitis tool from AWS-FPGA repo to design hardware kernels with HLS. I started the Hello World example and followed the instructions for Hardware simulation. Where do I find a statistic report that contains information such as hardware utilization, target frequency, latency, etc? Thanks

When I open any of my checkpoint dcps placed here, ex. /home/centos/src/project_data/aws-fpga/hdk/cl/examples/cl_dram_dma/build/checkpoints/ All of the nets and leaf cells show up as "<hidden>". IIRC I used to seeing the shell and "customer logic" showing up and being able to look at schematics of how the customer logic synthesized? Is there something I'm missing? Thanks

When I run $VITIS_DIR/tools/create_vitis_afi.sh, it prints an error "grep: /hdk/hdk_version.txt: No such file or directory". Looks like the issue is that the "script_dir" variable in shared/bin/set_common_env_vars.sh is not set before it is used. Therefore HDK_DIR environment is set to wrong value.

If I have this during linking: --sp multiexp_kernel_1.point_p:DDR\\[0:1\] Does this mean my kernel will be able to access both DDR banks? For example I need to consume 32GB of input data. It says this during linking: INFO: \\[CFGEN 83-0\] Port Specs: INFO: \\[CFGEN 83-0\] kernel: multiexp_kernel_1, k_port: point_p, sptag: DDR\\[0:1\] INFO: \\[CFGEN 83-2228\] Creating mapping for argument multiexp_kernel_1.point_p to DDR\\[0:1\] for directive multiexp_kernel_1.point_p:DDR\\[0:1\] And then the buffer I assign to \\[point_p\] can have a \\[vector_size_bytes\] that uses 32GB? cl::Buffer buffer_r1(context, CL_MEM_USE_HOST_PTR | CL_MEM_READ_ONLY, vector_size_bytes = 2 << 34,... Or would I need to create extra inputs and bridging logic to control access in the kernel + multiple buffers in host.cpp to get access to 32GB?

Hello, I'm trying to run Using-PCIM-Port example from https://github.com/awslabs/aws-fpga-app-notes/tree/master/Using-PCIM-Port Following the read me, I was able to Load AFI, (agfi-0d132ece5c8010bf7) build ATG drivers and by the time I install I hit on a Error sudo insmod atg_driver.ko slot=0x0f insmod: ERROR: could not insert module atg_driver.ko: Device or resource busy. dmesg logs: \[ 181.293259] IPv6: ADDRCONF(NETDEV_UP): ens3: link is not ready \[ 181.388658] IPv6: ADDRCONF(NETDEV_UP): ens3: link is not ready \[ 181.749638] IPv6: ADDRCONF(NETDEV_CHANGE): ens3: link becomes ready \[ 182.766973] tun: Universal TUN/TAP device driver, 1.6 \[ 182.771777] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> \[ 182.778610] virbr0: port 1(virbr0-nic) entered blocking state \[ 182.783989] virbr0: port 1(virbr0-nic) entered disabled state \[ 182.789778] device virbr0-nic entered promiscuous mode \[ 182.955985] virbr0: port 1(virbr0-nic) entered blocking state \[ 182.961290] virbr0: port 1(virbr0-nic) entered listening state \[ 182.966475] IPv6: ADDRCONF(NETDEV_UP): virbr0: link is not ready \[ 183.013277] virbr0: port 1(virbr0-nic) entered disabled state \[ 838.922911] Installing atg module \[ 838.926951] vendor: 1d0f, device: f001 \[ 838.931777] Enable result: 0 \[ 838.935241] xdma 0000:00:0f.0: BAR 0: can't reserve \[mem 0xc4000000-0xc5ffffff] \[ 838.943842] atg_driver: cannot obtain the OCL region How can I fix this ? I'm using a x16 card on centos. Edited by: TJ25 on Mar 30, 2020 9:02 AM

Hi Deep, I had launched up one F1.4x instance. the F1.4x has two fpga cards vs f1.2 which has just one. 1. If I just run one application, which fpga card will be used default? Or should I assign one FPGA to it --and how? 2. If I have multiple applications, then what fpga will be assigned to which fpga card, how can I do that? 3. Now I just already install ubuntu and vitis, and then build and installed the XRT (already install xrt.deb and aws-xrt.deb. Then by running xbutil scan, it reports one devic, which is not usable: ``` xbutil scan INFO: Found total 1 card(s), 0 are usable ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ System Configuration OS name: Linux Release: 4.15.0-1063-aws Version: #67-Ubuntu SMP Mon Mar 2 07:24:29 UTC 2020 Machine: x86_64 Model: HVM domU CPU cores: 16 Memory: 245842 MB Glibc: 2.27 Distribution: Ubuntu 18.04.4 LTS Now: Mon Mar 30 09:12:25 2020 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ XRT Information Version: 2.6.0 Git Hash: 0be8f75ca7e8a676ae5d385f453636c11567d584 Git Branch: master Build Date: 2020-03-30 08:22:33 XOCL: 2.6.0,0be8f75ca7e8a676ae5d385f453636c11567d584 XCLMGMT: unknown ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *[0] 0000:00:1d.0 xilinx_aws-vu9p-f1_dynamic_5_0(ID=0xabcd) user(inst=129) WARNING: card(s) marked by '*' are not ready, is MPD runing? run 'systemctl status mpd' to check MPD details. ``` Here is the mpd journal log (start from reboot, then I did a stop and restart mpd). ``` -- Reboot -- Mar 30 08:50:03 ip-172-31-19-142 systemd[1]: Started Xilinx Management Proxy Daemon (MPD). Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: started Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: aws: load default afi to 0000:00:1b.0 Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: found mpd plugin: /opt/xilinx/xrt/lib/libmpd_plugin.so Mar 30 09:18:05 ip-172-31-19-142 mpd[1573]: aws: load default afi to 0000:00:1d.0 Mar 30 09:19:10 ip-172-31-19-142 mpd[1573]: mpd caught signal 15 Mar 30 09:19:10 ip-172-31-19-142 systemd[1]: Stopping Xilinx Management Proxy Daemon (MPD)... Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: State 'stop-sigterm' timed out. Killing. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Killing process 1573 (mpd) with signal SIGKILL. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Main process exited, code=killed, status=9/KILL Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Failed with result 'timeout'. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: Stopped Xilinx Management Proxy Daemon (MPD). Mar 30 09:20:56 ip-172-31-19-142 systemd[1]: Started Xilinx Management Proxy Daemon (MPD). Mar 30 09:20:56 ip-172-31-19-142 mpd[9324]: started Mar 30 09:20:56 ip-172-31-19-142 mpd[9324]: found mpd plugin: /opt/xilinx/xrt/lib/libmpd_plugin.so Mar 30 09:20:59 ip-172-31-19-142 mpd[9324]: aws: load default afi to 0000:00:1b.0 ``` BTW, I tried source vitis_runtime_setup.sh, it reports some error as below, does that matter?? Note I had built the XRT package and installed the xrt.deb then installed aws-xrt.deb. ``` WARNING: 4.15.0-1063-aws does not match one of recommended kernel versions 3.10.0-862.11.6.el7.x86_64 3.10.0-693.21.1.el7.x86_64 3.10.0-957.1.3.el7.x86_64 3.10.0-957.5.1.el7.x86_64 3.10.0-957.27.2.el7.x86_64 3.10.0-1062.4.1.el7.x86_64 3.10.0-1062.9.1.el7.x86_64WARNING: Xilinx Runtime not validated against your installed kernel version. INFO: Xilinx Vivado version is 2019.2 INFO: XRT installed. proceeding to check version compatibility INFO: Installed XRT version : 2019.2:0be8f75ca7e8a676ae5d385f453636c11567d584 ERROR: 2019.2:0be8f75ca7e8a676ae5d385f453636c11567d584 does not match recommended versions ``` Thanks a lot! Edited by: macleonsh on Mar 30, 2020 1:59 AM

I used the create_vitis_afi.sh to create the awsxclbin file. However, when I check the image status using: aws ec2 describe-fpga-images --fpga-image-ids <afi-id> I see the state code as `pending`. How long should I expect it to be ready? If it is pending for a very long time, what should I do? I cannot find anything under the log folder on S3.

As of this morning I'm seeing a runtime error from xocc and vivado that I've never seen before. I created a fresh F1 instance and still see this running the helloworld_ocl example. Is this a known issue? /opt/Xilinx/SDx/2018.3.op2405991/bin/xocc -t sw_emu --platform /home/centos/src/project_data/aws-fpga/SDAccel/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm --save-temps -c -k vector_add -I'src' -o'xclbin/vector_add.sw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xo' 'src/vector_addition.cl' terminate called after throwing an instance of 'std::runtime_error' what(): locale::facet::_S_create_c_locale name not valid /opt/Xilinx/SDx/2018.3.op2405991/bin/loader: line 213: 6550 Aborted "$RDI_PROG" "$@" make: *** \[xclbin/vector_add.sw_emu.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xo] Error 134

Hi, I am adapting the _cl_dram_dma_ hdk example for my own project, and during the running of _aws_build_dcp_from_cl.sh_, I am encountering the DRC error below. I cannot find anywhere in the cl_ocl_slv module or instantiation that has the nets below, so I was hoping to get some insight into why the DRC is failing and how to go about fixing it. Thank you in advance. ``` Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcvu9p' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcvu9p' Attempting to get a license: PartialReconfiguration Feature available: PartialReconfiguration Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads ERROR: [DRC MDRV-1] Multiple Driver Nets: Net WRAPPER_INST/CL/CL_OCL_SLV/I9[0] has multiple drivers: WRAPPER_INST/CL/CL_OCL_SLV/pipe[0][0]_i_2/O, and WRAPPER_INST/CL/CL_OCL_SLV/pipe[0][0]_i_1__3/O. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port I2C_FPGA_MEM_R_SCL expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port I2C_FPGA_QSFP28_R_SCL expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 1 Errors, 2 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. ```

Is it possible to directly transfer data via p2p DMA from one of the NVMe SSDs to/from the FPGA? In a non-cloud environment, it does work if your PCIe root complex / PLX switch supports peer-2-peer PCIe thanks to the p2pDMA driver. https://www.kernel.org/doc/html/latest/driver-api/pci/p2pdma.html I would like to evaluate if such a setup could work in an AWS f1 instance.

Hi, can I assume that in the sh_cl_apppf_irq_ack interface, at most one bit is set? Or is it possible that in a single clock cycle multiple bits are set? Let's say I send a request on cl_sh_apppf_irq_req for two interrupts in the same clock cycle (I suppose this is supported, if not please say so). Will both interrupts then ack'ed also in a later, but also same clock cycle? Or will they always be ack'ed one after another? So, two questions: - How many bits **may** be set in cl_sh_apppf_irq_req in the same clock cycle? - How many bits **can** be set in sh_cl_apppf_irq_ack? Thanks!

Hello. Is it possible to access the FPGA from multiple threads or processes ? - Can I attach to the same FPGA from multiple processes at once? - Can I open a DMA queue from two or more processes and transfer data to/from the same FPGA ? - Can I use fpga_pci_peek() / fpga_pci_poke() from multiple threads in a process attached to the FPGA ? Example of utilization : I have 4 accelerators on the FPGA, each using a DDR4 memory and each having their own memory space (for control through OCL bus and for DDR4 access through PCIS bus) in the memory map. Can 4 different processes each use an accelerator through the provided interfaces safely ? Each attach to the same FPGA card on the same slot, each opening a DMA queue, or peeking/poking the OCL bus. I understand the PCIS and OCL bus will be shared and that a process may have to wait for it to be ready for a call to e.g., to fpga_pci_poke() to be completed. Is this situation possible / safe ? Thank you for your time. Regards. Rick Edited by: rwe on Jun 26, 2019 5:55 AM Added example.

Hi, for our project, we have a toolchain that tries to find the optimal frequency for a design. It does so by configuring a Clocking Wizard, building a bitstream and then evaluate the timing report. This works perfectly on our on-premise hardware, but not on the F1 instances. Placing a Clockwiz/MMCM in the CL leads to an error about sub-optimal placement of a MMCM-BUFGCE-MMCM cascade. This error can be demoted to a warning. But unless the output of the MMCM is a multiple of the input clock (like 62.5 MHz from the clk_extra_a1 -> 250 MHz output), there are timing violations. While the design works for 250 Mhz, using 225 MHz causes a WNS of of about -0.976. I tried changing the buffer settings, or even a PLL instead of the MMCM, but none of this works. I understand that I'm limited with my options, as I have no access to the Shell reconfiguration area, so I cannot place my MMCM in the recommended way ("The MMCM-BUFGCE-MMCM cascade pair can use the dedicated path between them if they are placed in vertically adjacent clock regions and in the same column (LEFT/RIGHT) of the device."). Is there any other supported way? Why doesn't the shell just expose a differential clock to the CL?

I ran into a couple of issues with the python script below in the aws-fpga repository on Ubuntu 16.04 $./SDAccel/examples/xilinx_2018.3/utility/parsexpmf.py 1. It uses #!/bin/env, which doesn't exist on Ubuntu by default. 2. It uses Python2 print syntax print vbnv(root) ^ SyntaxError: invalid syntax Is there a plan to make it compatible with Ubuntu and Python3 friendly? Thanks, Jim

Hi , I am creating a project with a pblock drawn in SLR2 and when i implement it , I am getting the following errors in the place design stage : ERROR: (DRC HDPR-6) Logic illegally placed: Cell 'WRAPPER_INST/SH/SH/RC_AXISTR_REG_SLICE/inst/axisc_register_slice_0/gen_AB_reg_slice.payload_a_reg(186)' is placed at site 'SLICE_X159Y249' which belongs to reconfigurable Pblock 'pblock_SH'. This cell is not part of the reconfigurable logic assigned to this Pblock, and should not be placed at this site ERROR: (DRC HDPR-12) A Partition Pblock cannot reference more than one partition: The Pblock 'pblock_SLR2' references more than one partition instance. The Pblock references both partition instance 'WRAPPER_INST/CL' and partition instance 'WRAPPER_INST/SH'. I have created the Pblock through following commands in xdc(cl_pnr_usr.xdc) file create_pblock pblock_SLR2 resize_pblock (get_pblocks pblock_SLR2) -add {CLOCKREGION_X0Y11:CLOCKREGION_X5Y14} resize_pblock (get_pblocks pblock_SLR2) -add {CLOCKREGION_X0Y10:CLOCKREGION_X2Y10} set_property PARENT pblock_CL (get_pblocks pblock_SLR2) Can anyone please suggest what is going wrong which is producing this error?

Hello. I am trying to add an ILA to check the behavior of an AXI bus in my design. My design works in simulation but gets stuck on the FPGA. In order to debug this I want to check an AXI bus with an ILA. I used the following document as a reference : <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md> And the "hello_world" design as an example. I instanciated the debug bridge in my top with the following lines : ``` // Debug Bridge cl_debug_bridge CL_DEBUG_BRIDGE ( .clk(clk_main_a0), .S_BSCAN_drck(drck), .S_BSCAN_shift(shift), .S_BSCAN_tdi(tdi), .S_BSCAN_update(update), .S_BSCAN_sel(sel), .S_BSCAN_tdo(tdo), .S_BSCAN_tms(tms), .S_BSCAN_tck(tck), .S_BSCAN_runtest(runtest), .S_BSCAN_reset(reset), .S_BSCAN_capture(capture), .S_BSCAN_bscanid_en(bscanid_en) ); ``` I created an ILA using the IP catalog and a board diagram, the board diagram is because the ILA names the input ports probeXX instead of the AXI signal names and with the board diagram I can make a wrapper with the correct names. I added the ILA in the design and got the following errors on synthesis : ``` INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p' INFO: [Vivado_Tcl 4-550] User specified maximum number of URAM that can be cascaded is 2 CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_in.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_in.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_in.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs_core.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_core.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs_core.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_vl_rfs.v' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17187 ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5838] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5867] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5900] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5934] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9887] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9916] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9949] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9983] Failed to read verilog '/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v' INFO: [Common 17-83] Releasing license: Synthesis 6 Infos, 17 Warnings, 4 Critical Warnings and 9 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details while executing "source -notrace ./synth_${CL_MODULE}.tcl" invoked from within "if {${cl.synth}} { source -notrace ./synth_${CL_MODULE}.tcl }" (file "create_dcp_from_cl.tcl" line 196) INFO: [Common 17-206] Exiting Vivado at Mon May 27 15:52:58 2019... ``` There is a conflict between the sources used by the debug bridge IP and my ILA IP. I followed the instructions in <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md> Embedding Debug Cores in the CL. But I could not find how to solve this. Do you have any suggestion on how to solve this ? Thank you very much. Best Regads.

Hi, I am about to build a new on-premises server, to develope with AWS HDK 1.4.8+ (2018.3) release, and wondering what is the recommended Linux OS version?. What are the minimun system requirements? Thanks, Gabi Edited by: gabima on May 19, 2019 4:51 AM

Hi, the Shell specification says: > **This interface uses single clock pulses for the req/ack.** The CL asserts (active high) cl_sh_apppf_irq_req\[x] for a single clock to assert the interrupt request to the SH. The SH will respond with a single clock pulse on sh_cl_apppf_irq_ack\[x] to acknowledge the interrupt. As I understand it, the Shell uses the Xilinx PCIe DMA core (XDMA) for DMA and user interrupts. Xilinx PG195 says about the user interrupts: >After a usr_irq_req bit is asserted, it **must remain asserted until the corresponding usr_irq_ack bit is asserted**. The usr_irq_ack bit assertion indicates the requested interrupt has been sent on PCIe. For MSI-X, once this ack has been observed, the usr_irq_req bit can be deasserted. Does the shell have additional logic to handle this requirement? I.e. does my CL need to send a single clock pulse as stated in the shell specification or must the CL assert the request line until it got ack'ed?

Hi, I am simulating my design after connecting it to the DDRB, but ddrb_is_ready doesnt get asserted. I am using the IPI flow. I have customized the F1 IP to enable DDRB interface and connected the DDRB AXI interface and the ddrb_is_ready signal to my design. Now when I run the test, ddrb_is_ready is not asserted. I have ran the simulation for more than 280us, but don't see the ddrb_is_ready going up. Below is the instruction sequence from my test.sv. What am I missing. initial begin tb.power_up(); tb.nsec_delay(5000); //Read the status register (original wait for 400ns then enable, #40000) tb.peek_bar1(0, `IP_STATUS_REG, rdata, 6'h0); // allow memory to initialize tb.nsec_delay(270000); $finish; end

Hello I recently updated my on-premise development tools to 2018.2, and the rtl_kernel examples are failing with error against the gen_XXX.tcl script. For example, for the following example: aws-fpga/SDAccel/examples/xilinx_2018.2/getting_started/rtl_kernel/rtl_vadd when I run this make command: make check TARGETS=hw_emu DEVICES=$AWS_PLATFORM_DYNAMIC_5_0 all I get the following error: ================================== mkdir -p xclbin /extra/opt/Xilinx/Vivado/2018.2.op2258646/bin/vivado -mode batch -source scripts/gen_xo.tcl -tclargs xclbin/vadd.hw_emu..xo vadd hw_emu ****** Vivado v2018.2.op (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source scripts/gen_xo.tcl # if { $::argc != 4 } { # puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n" # puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n" # exit # } ERROR: Program "scripts/gen_xo.tcl" requires 4 arguments! Usage: scripts/gen_xo.tcl <xoname> <krnl_name> <target> <device> INFO: \[Common 17-206] Exiting Vivado at Mon Apr 1 15:35:37 2019... mkdir -p xclbin /extra/opt/Xilinx/SDx/2018.2.op2258646/bin/xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o xclbin/vadd.hw_emu..xclbin -t hw_emu --platform /home/tytra/aws-fpga/SDAccel/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm xclbin/vadd.hw_emu..xo ****** xocc v2018.2_AR71715 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ERROR: \[XOCC 60-602] Source file does not exist: /home/tytra/aws-fpga/SDAccel/examples/xilinx_2018.2/getting_started/rtl_kernel/rtl_vadd/xclbin/vadd.hw_emu..xo ERROR: \[XOCC 60-623] Unsupported input file type specified. make: *** \[xclbin/vadd.hw_emu..xclbin] Error 1 =================================== Can someone kindly advise on this? I get a similar error for any example in the rtl_kernel folder. Many thanks, Waqar.

Hi, I'm trying to integrate the Shell into an existing project, which already makes heavy use of scripts to build the design. So I thought it might be easier to only pick the relevant pieces from the AWS TCL scripts and integrate them into my project. Everything worked fine so far, until I reached this error during implementation phase: ``` Memory Core Error - [system_i/host/f1_inst/inst/gen_mem.sh_ddr_0/ddr_cores.DDR4_2] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures. ERROR: [Mig 66-99] Memory Core Error - [system_i/host/f1_inst/inst/gen_mem.sh_ddr_0/ddr_cores.DDR4_2] Port(s) S_SH_m_d_clk_dn[0],S_SH_m_d_clk_dp[0],S_SH_m_d_ma[0],S_SH_m_d_ma[1], [...] is/are not placed. Assign all ports to valid sites. ``` I searched where the sys_clk and other ports are created and found - nothing. Are those files missing from the HDK? Are end users not supposed to synthesize/implement the Shell on their own? Is there any way or are we confied to use the provided SH_CL_BB_routed.dcp?

Hi, Is there example or tutorial for burst mode of AXI-4? I am trying to use burst mode to write bulk data to DRAMs. Apart from burst signals on FPGAs, I did not find which c program or function I should use. Thanks! Sam

Hi , I am creating a project in which oscillators are involved . I do the implementation on my system and then create the tar file and upload it to the AWS instance for AFI image creation. But it throws the following error : " ERROR: (DRC LUTLP-1)Combinatorial Loop Alert: 2 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE (get_nets <myHier/myNet>)'." I tried setting the property as suggested above in the error comand but still i am not able to bypass this DRC error. Any suggestions on this issue? Thanks Prigish

Since some of the later versions, sourcing hdk_setup.sh checks whether patch AR71715 is installed and if not, installs it. But: after it is installed, hdk_setup does no longer recognize the installed version as valid, i.e.: ``` INFO: Setting up environment variables INFO: Base vivado version is Vivado v2018.2_AR71715 (64-bit) ; Checking if patch AR71715 needs to be installed INFO: Using Vivado v2018.2_AR71715 (64-bit) ERROR: Vivado v2018.2_AR71715 (64-bit) is not supported by this HDK release. ERROR: Supported versions are: Vivado v2017.4 (64-bit) Vivado v2017.4.op (64-bit) Vivado v2018.2_AR71275_op (64-bit) Vivado v2018.2.op (64-bit) Vivado v2018.2 (64-bit) ``` Note I'm using an on premise version of Vivado and installed the patch using the XILINX_PATH method \[1] I think hdk_setups hould recognize **v2018.2_AR71715** as valid version. Or am I mistaken? \[1] https://www.xilinx.com/support/answers/66722.html

Hello, I seem to have a design that is barely routable. I found that if I reduce the AXI master address width to 16 bits it routes (but does not function). At 64 bits it does not route. I only need to transfer 528 bytes of data to/from the kernel. Is it possible to restrict memory to a much smaller address space? I know the documentation says 64 bits is required but want to see if there are any workarounds. I don't think using scalars would work because they cannot be read back. Thanks!

My synthesis runs have been working fine until a recent set of innocuous modifications to the source. All of a sudden I'm getting errors in synthesis that have to do with an axi_register_slice I have in my cl_top.sv. I've triple checked the source is there and deleted the encrypted output. Has anyone else run into this problem? Does anyone have any ideas I can try? I'm unfortunately not able to share my source. The errors happen in RTL Elaboration and look like the following: INFO: \[Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189] Parameter C_FAMILY bound to: virtexuplus - type: string Parameter C_DATA_WIDTH bound to: 109 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189] ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:2300] ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v:58] ERROR: \[Synth 8-5809] Error generated from encrypted envelope. \[/home/centos/cl_base/build/src_post_encryption/cl_top.sv:17] Thanks in advance, -Jack

Hello, I see there is a new feature in xocc to synthesize and implement and RTL kernel in Vivado and feed the result back into to the xocc flow (at least, that is how I understand it). When I try to do this in the F1 development AMI I get an error that the kernel.xml file is not present. It looks like there is a directory tree in _x/link/int that is not yet populated by the makefiles in the rtl_vadd example. Is this flow expected to work? Thanks!

While compiling my desing with the latest version of HDK Kit (HDK_VERSION=1.4.7) and Vivado version 2018.2, I get the following error. ERROR: \[XSIM 43-3316] Signal SIGSEGV received. I also found another user having the same error with an hdk example design itself as in thread below. I am attaching tail my elaborate.log below to provide another datapoint. https://forums.aws.amazon.com/thread.jspa?messageID=890695&#890695 ------------------------------------------------------------------------------------- WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:475] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:476] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:477] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:478] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:479] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:480] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:481] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:482] WARNING: \[VRFC 10-727] function device_bdr_ld has no return value assignment \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:396] WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2527] WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2685] WARNING: \[VRFC 10-727] function match_char_after has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4562] WARNING: \[VRFC 10-727] function match_range has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4575] WARNING: \[VRFC 10-727] function track_value_context has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:5545] WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1571] WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1573] WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:182] WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:195] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:117] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:118] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/len_model_mgmt.sv:320] WARNING: \[VRFC 10-597] element index 16 into valid_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:147] WARNING: \[VRFC 10-597] element index 16 into sign_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:148] WARNING: \[VRFC 10-597] element index 16 into dividend_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:149] WARNING: \[VRFC 10-597] element index 16 into dividend_lo_bits_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:150] WARNING: \[VRFC 10-597] element index 16 into divisor_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:151] WARNING: \[VRFC 10-597] element index 16 into remainder_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:152] WARNING: \[VRFC 10-597] element index 16 into quotient_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:153] WARNING: \[VRFC 10-597] element index 16 into division_done_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:154] Completed static elaboration WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 855 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored. WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1753 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored. INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2527, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2685, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv ERROR: \[XSIM 43-3316] Signal SIGSEGV received. "elaborate.log" 159L, 29695C

Hi, I am setting up on-prim development tools for AWS FPGA development. I installed Centos7.6 and downloaded the AWS HDK Kit. Followed all the steps of sourcing the hdk_setup.sh and setting up CL_DIR variable. However Vivado is not able to find aws::make_ipi. I get the following error. aws::make_ipi invalid command name "aws::make_ipi" My first thought was that it might have to do something with some of the Vivado features I skipped installing (like SDK). So I reinstalled Vivado System version with all the features and tried again. Still same thing. I have done this many times on AWS FPGA Developer AMI, but doing on premise for the first time. Also, the AWS HDK Kit has been updated since I last successfully compiled. Is there any pre-requisite or setting I am missing? or is it something chanaged with the new verseion of AWS HDK Kit. Thanks fpgamagic

Installation of the **Xilinx Runtime** on a clear **Amazon Linux 2** instance (which is RedHat based) leads to OpenCL runtime errors. **Xilinx Runtime (XRT) 2018.2_XDF.RC5** Installation instructions: https://github.com/aws/aws-fpga/blob/master/hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-xilinx-runtime-xrt-20182_xdfrc5 _Prerequisites_: Extra Packages for Enterprise Linux (EPEL) ``` sudo amazon-linux-extras install -y epel ``` ``` curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm sudo yum install -y xrt_201802.2.1.0_7.5.1804-xrt.rpm sudo yum install -y xrt_201802.2.1.0_7.5.1804-aws.rpm ``` Example application: ``` #include <stdio.h> #include <CL/opencl.h> int main(){ cl_uint num_platforms; cl_int errcode_ret = clGetPlatformIDs(0, NULL, &num_platforms); if (errcode_ret != CL_SUCCESS){ fprintf(stderr, "Error: clGetPlatformIDs (%d)\n", errcode_ret); return EXIT_FAILURE; } printf("Info: %d opencl platform(s) found!", num_platforms); return EXIT_SUCCESS; } ``` Makefile: ``` SRCS = test.cpp OBJCTS = $(SRCS:.cpp=.o) EXE=test CC = g++ -Wall CFLAGS = -I${XILINX_XRT}/include LFLAGS = -L${XILINX_XRT}/lib -lxilinxopencl all: ${OBJCTS} ${CC} ${OBJCTS} ${LFLAGS} -o ${EXE} ${RM} ${OBJCTS} %.o: %.cpp ${CC} ${CFLAGS} -c ${<} -o ${@} clean: ${RM} ${OBJCTS} ${EXE} ``` 3 _sequential_ runs: $ ./test Segmentation fault $ ./test Segmentation fault $ ./test terminate called after throwing an instance of 'std::bad_alloc' what(): std::bad_alloc Aborted The problem must be related to boost library dependency! (Our JVM application stated **libboost.so** as the problematic frame.) **Note** that on a CentOS machine the same XRT installation works smoothly.

I am getting the following errors, while trying to simulate my design with AWS shell. It seems like the arch_package, proj_package declaration is missing. Where are they supposed to be declared. I already checked the the init.tcl file is being sourced and it contains the following lines: set AWSINSTALL "C:/AWS_Repo/aws-fpga" source $AWSINSTALL/hdk/common/shell_v04261818/hlx/hlx_setup.tcl Errors from the log: INFO: \[VRFC 10-2263] Analyzing SystemVerilog file "C:/AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_rdimm_wrapper/ddr4_db_delay_model.sv" into library xil_defaultlib INFO: \[VRFC 10-311] analyzing module ddr4_db_delay_model INFO: \[VRFC 10-2263] Analyzing SystemVerilog file "C:/AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv" into library xil_defaultlib ERROR: \[VRFC 10-91] arch_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTable.sv:5] INFO: \[VRFC 10-311] analyzing module StateTable ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:1553] ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:1554] ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:2950] ERROR: \[VRFC 10-91] MAX_ROW_ADDR_BITS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:14] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:14] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:15] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:15] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:27] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:27] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:28] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:28] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:29] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:29] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:30] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:30] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:31] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:31] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:32] INFO: \[#UNDEF] Sorry, too many errors..

While running a build, I got the error "EXCEPTION_ACCESS_VIOLATION". I checked the log pointed to by the message and it was empty. I closed Vivado and restarted in a fresh directory. But this time, Vivado crashed, just disappeared without any warning or message. After this, I tried multiple settings, and even recompiling some old projects which have been compiled successfully many times before,but Vivado just keeps crashing. The Vivado is starting to execute the synth_design task when this happens.In last compilation, the last message in Vivado log before it crashed was: Launching runs with argument(s) impl_1 -jobs 20 INFO: \[IP_Flow 19-4838] Using cached IP synthesis design for IP cl_clk_wiz_0_0, cache-ID = e74bb25c0f1c1add. I am using Vivado 2017.4op on Windows 10. Has anyone else seen this crash? Are there any known workarounds or fixes for this.

Hi, I am using the cl_sde example in my design, including its IPs. I use vivado v2018.2_AR71275_op (included in FPGA Developer AMI v1.5.0). The problem: I can't generate the included sde IPs, due to a different vivado version. For instance, I got this in a attempt to generate the ila_axi4 ip: CRITICAL WARNING: \[filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/centos/aws-fpga/hdk/cl/examples/cl_sde/ip/ila_axi4/ila_axi4.xci Locked reason: * IP definition 'ILA (Integrated Logic Analyzer) (6.2)' for IP 'ila_axi4' (customized with software release 2017.4.op) has a different revision in the IP Catalog. Any hint/help with resolving this will be much appreciated. Thanks, gabima

Hi Amazon Team, As requested in the previous thread:<https://forums.aws.amazon.com/thread.jspa?messageID=887224&#887224> I am unable to source the hdk_setup script with maintaining the kernel version 3.10.0-862.11.6.el7.x86_64 and AMI version 1.5. When sourcing the script i get this error: **NFO: Setting up environment variables** **ERROR: Please install/enable Vivado.** **ERROR: If you are using the FPGA Developer AMI then please request support.** Additional Info: Launching the _vivado -mode batch_ command gives: **$ vivado -mode batch** **terminate called after throwing an instance of 'std::runtime_error'** **what(): locale::facet::_S_create_c_locale name not valid** **/opt/Xilinx/Vivado/2018.2.op2258646/bin/loader: line 194: 2270 Aborted "$RDI_PROG" "$@"** Information: **Kernel version** : 3.10.0-862.11.6.el7.x86_64 **AMI version** : 1.5.0 **hdk version** : HDK_VERSION=1.4.6 Please advise. Thanks,

Hello, if I understand the architecture correctly, I can only have 16 interrupts \[1]. Is this correct? For my current project, it would be good to have 128+ interrupts. Is there any way to achieve this? Except for aggregating interrupts and additional checking on the host/software side. \[1] https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#interrupts Regards and thanks.

Hi, Does anybody know how to get utilization and timing reports when using SDAccel + RTL flow?. I was trying to use **--report estimate** on **xocc** but it is not reporting anything on the **system_estimate.xtxt** file. I think this option only works for OpenCL kernels and not for RTL's ones? Thanks!