Questions tagged with FPGA Development
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I cannot pop up GUI when I use mobaxterm if I set emulation debug=gui in Amazon AMI here https://aws.amazon.com/marketplace/pp/prodview-hxbanceez6tso.
It should pop up if I set it when I do HW...
1
answers
0
votes
72
views
asked 14 days agolg...
Hi,

Look at the above image. From **module A**, a gated clock is going to **module B**. We found that **module...
1
answers
0
votes
84
views
asked 24 days agolg...
Hi,
I was trying to read a memory from FPGA using DMA read and I got the following output.
a4,
e,
25,
3c,
28,
85,
dc,
5,
**a4,
e,
25,
3c,
28,
85,
dc,
5**.
8 bytes are repeated here.
The expected...
Accepted AnswerFPGA Development
4
answers
0
votes
115
views
asked 2 months agolg...
DMA restrictionslg...
Hi,
I want to write two different registers/memory parallelly using DMA. I tried using multithreading concept. But writing is not happening as expected. I mean there is a time delay. How to avoid it?...
1
answers
0
votes
81
views
asked 2 months agolg...
Hi,
I want to store 500 MB of data in DDR and it should be feed to my design as 64 bit data continuously using 40 MHz clock (Note: 40 MHz clock is generated using MMCM). How to achieve this.?
Thank...
Accepted AnswerFPGA Development
1
answers
0
votes
87
views
asked 2 months agolg...
Hi,
we are seeing performance drop when we access specific address pattern from DDR. Please find the below details.
in a single test we read same address repeatedly as mentioned below
rd_addr is...
1
answers
0
votes
151
views
asked 3 months agolg...
Hi there,
Is there a way that CL can control the XDMA inside the Shell in the AWS F1? I have a usecase where CL needs to setup a DMA transfer from internal memory to Host.
A separate question, Is...
1
answers
0
votes
106
views
asked 3 months agolg...
XRT ERROR : failed to load xclbin : input output error hello_world tutorial on AWS F1 / AMI 1.12.2lg...
I encountered an error during the official tutorial. (https://github.com/aws/aws-fpga/blob/master/Vitis/README.md)
I followed the tutorial in
AWS F1(f1.2xlarge) instance / oregon
FPGA Developer AMI...
Accepted AnswerFPGA Development
3
answers
0
votes
159
views
asked 3 months agolg...
I needed a phase-shifted (relative to the clk_main_a0) clock for my CL, and I implemented that using an MMCME4_ADV in my design. I ran into the well-known sub-optimal placement issues. When I did this...
1
answers
0
votes
101
views
asked 3 months agolg...
Hi,
I have to connect my design with ARM processor and I have to create 2 AFIs with the same design. One is transmitter and another is receiver. But both have to be configured in a different way so...
Accepted AnswerFPGA Development
1
answers
0
votes
107
views
asked 3 months agolg...
Hi,
Getting the following error while implementing my custom logic.
ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net...
Accepted AnswerFPGA Development
3
answers
0
votes
193
views
asked 5 months agolg...
I am trying to do some optimization for network traffic handling by utilizing FGPA acceleration on AWS [F1?].
Per my understanding the F1 service is based on Xilinx Alveo SmartNIC hardware.
So my...
2
answers
0
votes
156
views
asked 5 months agolg...