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Questions tagged with FPGA Development

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Stuck at Hello World synthesis stage

Hi. I am using FPGA Developer AMI 1.11.0 and was running hello_world example from https://github.com/aws/aws-fpga/blob/master/Vitis/README.md, using "make all TARGET=hw DEVICE=$AWS_PLATFORM" I am using m5.xlarge on us-west-1. Unlike the run using previous AMI version, it no longer progresses after the point: ============================== \[11:44:52] Run vpl: Step create_project: Completed \[11:44:52] Run vpl: Step create_bd: Started \[11:45:23] Run vpl: Step create_bd: Completed \[11:45:23] Run vpl: Step update_bd: Started \[11:45:23] Run vpl: Step update_bd: Completed \[11:45:23] Run vpl: Step generate_target: Started \[11:46:36] Run vpl: Step generate_target: Completed \[11:46:36] Run vpl: Step config_hw_runs: Started \[11:46:41] Run vpl: Step config_hw_runs: Completed \[11:46:41] Run vpl: Step synth: Started ============================== When I type "top" - vivado CPU utilization goes down to near 1%. (not killed - just not working) So I looked at "./_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/vivado.log", and it has ended at the point ============================== \[Mon Sep 6 11:46:44 2021] Launched my_rm_synth_1... Run output will be captured here: /home/ec2-user/src/project_data/aws-fpga/Vitis/examples/xilinx_2021.1/hello_world/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/link/vivado/vpl/prj/prj.runs/my_rm_synth_1/runme.log \[Mon Sep 6 11:46:44 2021] Waiting for my_rm_synth_1 to finish... ============================== From comparing with logs with previous version, I think Vivado should get launched at this point to do synthesis, but it is not happening. I know it is a vague description of the problem, but is there some commands I can try to figure why it has stopped working? I suppose Vivado program is waiting for some routines to finish, and they are not responding back - but not sure what to check. Thanks.
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asked 9 months ago

Cannot launch Vitis HLS Gui mode with FPGA Developer AMI 1.10.0

Hi. I was trying to launch Vitis HLS GUI with FPGA Deveoper AMI 1.10.0. I did "git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR", and then "cd $AWS_FPGA_REPO_DIR" and then "source vitis_setup.sh" and then "source /opt/Xilinx/Vitis_HLS/2020.2/settings64.sh" but when I launch "vitis_hls", I get message: ================================= ****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit) **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020 **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source /opt/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace INFO: \[HLS 200-10] Running '/opt/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls' INFO: \[HLS 200-10] For user 'centos' on host 'ip-xxx-xx-xx-xx.ap-northeast-2.compute.internal' (Linux_x86_64 version 3.10.0-1160.6.1.el7.x86_64) on Tue Jul 13 06:47:43 UTC 2021 INFO: \[HLS 200-10] On os "CentOS Linux release 7.9.2009 (Core)" INFO: \[HLS 200-10] In directory '/home/centos' INFO: \[HLS 200-10] Bringing up Vitis HLS GUI ... INFO: \[Common 17-206] Exiting vitis_hls at Tue Jul 13 06:47:48 2021... ============================================== So, pretty much no information on why it is not launching. I can launch xeyes, so I don't think it is X problem. If there additional dependencies I should install for Vitis HLS GUI, could anyone tell me the list?
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asked 10 months ago

Help: fpga-clear-local-image not found

I am following the HDK getting started guide, in particular I am trying to execute the " <https://github.com/aws/aws-fpga/blob/master/hdk/README.md#how-to-create-an-amazon-fpga-image-afi-from-one-of-the-cl-examples-step-by-step-guide>" for the hello world example. I have successfully executed the first part - building the custom logic and publishing my new AFI. I have obtained the AFI ID and the AGFI ID. I have confirmed by executing `aws ec2 describe-fpga-images ` my AFI is available and I have verified it is in the bucket. The second part of the guide is about "how to load and test a registered AFI from withing an F1 instance". I have created an f1.2xlarge instance using the Centos FPGA Developer AMI. The welcome message is > login as: centos > Authenticating with public key "imported-openssh-key" > Last login: Thu Feb 25 15:40:14 2021 from 72-21-196-65.amazon.com > ___ ___ ___ _ ___ _____ __ _ __ __ ___ > | __| _ \/ __| /_\ | \| __\ \ / / /_\ | \/ |_ _| > | _|| _/ (_ |/ _ \ | |) | _| \ V / / _ \| |\/| || | > |_| |_| \___/_/ \_\ |___/|___| \_/ /_/ \_\_| |_|___| > AMI Version: 1.10.0 > Xilinx Version: 2020.2 > Readme: /home/centos/src/README.md > AMI Release Notes: /home/centos/src/RELEASE_NOTES.md > GUI/Cluster setup: https://github.com/aws/aws-fpga/blob/master/developer_resources > Developer Support: https://github.com/aws/aws-fpga/blob/master/README.md#developer- support > Centos Common code: /srv/git/centos-git-common > Xilinx XRT source: https://github.com/Xilinx/XRT Now, the instructions read: > git clone https://github.com/aws/aws-fpga.git $AWS_FPGA_REPO_DIR > cd $AWS_FPGA_REPO_DIR > source sdk_setup.sh (small aside: it would be best IMHO to provide the snipped with the definition of `$AWS_FPGA_REPO_DIR` again; the wording instructs to launch a new VM so I think definition cannot be assumed). So far everything look ok. I also ran `aws configure` as instructed. OK. Next step would be `sudo fpga-clear-local-image -S 0` This is what happens in reality: > \[centos@fpgadevc aws-fpga] sudo fpga-clear-local-image -S 0 > sudo: fpga-clear-local-image: command not found Related FPGA commands don't seem to work either. I don't really know where to find them but I was more focused in going by the book for now. I have tried to understand why those commands don't work and I am so far out of clues. What did I miss? Edited by: MaxDZ8 on Jul 4, 2021 9:02 AM - fix some layout Edited by: fixed more formatting woes.
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asked a year ago

Error generating an AFI with an .xclbin created with Vitis 2020.2

Hi I am getting an error when I try create an AFI with a 2020.2 Vitis .xclbin. I'm using aws-fpga v1.4.19. It seems like Vivado 2020.1 is being used. #----------------------------------------------------------- # Vivado v2020.1 (64-bit) # SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 # IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 # Start of session at: Sat Apr 10 14:48:42 2021 # Process ID: 11292 # Current directory: /home/builder/scripts # Command line: vivado -mode batch -source ingest.tcl # Log file: /home/builder/scripts/vivado.log # Journal file: /home/builder/scripts/vivado.jou #----------------------------------------------------------- source ingest.tcl # set userDCP "../checkpoints/SH_CL_routed.dcp" # set awsDCP "../checkpoints/SH_CL_BB_routed.dcp" # set awsDCPStripped "../checkpoints/SH_CL_BB_stripped.dcp" # set powerDefaultRPT "../reports/power_report.default.rpt" # set powerStaticRPT "../reports/power_report.static.rpt" # set timingRPT "../reports/SH_CL_final_timing_summary.rpt" # set ioRPT "../reports/report_io.rpt" # set partialBIT "../bitstreams/SH_CL_final_pblock_CL_partial.bit" # set partialLTX "../bitstreams/SH_CL_final_pblock_CL_partial.ltx" # set CL_PATH WRAPPER_INST/CL # puts "Ingest start time: \\[\[clock format \[clock seconds\] -format {%a %b %d %H:%M:%S %Y}\]\]" Ingest start time: \[Sat Apr 10 14:51:01 2021\] # set_param hd.supportClockNetCrossDiffReconfigurablePartitions 1 # set_param hd.platformVerifyCachedRun false # check_integrity $userDCP INFO: \[Vivado 12-5531\] Integrity check successful: /home/builder/checkpoints/SH_CL_routed.dcp check_integrity: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2181.945 ; gain = 0.004 ; free physical = 66549 ; free virtual = 89717 # set_msg_config -severity INFO -suppress # set_msg_config -severity STATUS -suppress # set_msg_config -severity WARNING -suppress CRITICAL WARNING: \[Common 17-1355\] You are suppressing all messages of type 'WARNING'. You may potentially disregard important DRC, CDC, and implementation messages that can negatively impact your design. If this is not desired, please run 'reset_msg_config -suppress -severity {WARNING}' to undo this change. # set_msg_config -id {Chipscope 16-3} -suppress # set_msg_config -string {AXI_QUAD_SPI} -suppress # puts "Opening user DCP $userDCP: \\[\[clock format \[clock seconds\] -format {%a %b %d %H:%M:%S %Y}\]\]" Opening user DCP ../checkpoints/SH_CL_routed.dcp: \[Sat Apr 10 14:51:09 2021\] # open_checkpoint $userDCP ERROR: \[Runs 36-378\] The checkpoint '/home/builder/checkpoints/SH_CL_routed.dcp' was created with 'Vivado v2020.2 (64-bit)', and cannot be opened in this version. Edited by: Yaniv42 on Apr 10, 2021 8:51 AM
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asked a year ago

awssak program fails in AMI 1.8.1 and 1.9.1

We have two xpfm setup (basically two different versions of the F1 shell) and we have generated bitfiles with them. The name of these two xpfm files are: * xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm *xilinx_aws-vu9p-f1_shell-v04261818_201920_2.xpfm I believe the latter is the one which works with Vitis 2019.2 and later versions. When we program either of the bitfiles on an F1.2xlarge instance with AMI 1.7.1 (FPGA Developer AMI - 1.7.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-073c0053d4be15233.4 - ami-0c9c61319a32e0692) it passes. But when we program either of the bitfiles on F1.2xlarge instance with AMI 1.8.1 (FPGA Developer AMI - 1.8.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0c90eb898f6c9f1bd.4 - ami-0209388abb64ef69c) or AMI 1.9.1 (FPGA Developer AMI - 1.9.1-40257ab5-6688-4c95-97d1-e251a40fd1fc-ami-0c3a51e8e73a7fa94.4 - ami-03d255ca72d04ce3e) they fail with the following error messages: **root@ip-172-31-4-120 ~# awssak program -p /tmp/binary_container_1_dynamic.awsxclbin** **xclProbe found 1 FPGA slots with xocl driver running** **INFO: Found 1 device(s)** **IOCTL DRM_IOCTL_XOCL_READ_AXLF Failed: -1** **ERROR: awssak program failed.** For newer version bitfile, dmesg shows the following errors: **\[Sat Feb 20 00:47:28 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: did not find platform dtb** **\[Sat Feb 20 00:47:28 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: Failed to download xclbin, err: -22** and for the older version bitfile, dmesg shows the following error: **\[Sat Feb 20 00:47:18 2021] xocl 0000:00:1d.0: xocl_read_axlf_helper: Failed to download xclbin, err: -110** Can you please guide us why this is happening? Edited by: shahrzad on Mar 3, 2021 11:52 AM
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asked a year ago

vivado crush

Hey, I'm connecting to my F1 instance using SSH when trying to start vivado I get: ***** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. start_gui Exception in thread "main" java.lang.UnsatisfiedLinkError: /opt/Xilinx/Vivado/2020.1/tps/lnx64/jre9.0.4/lib/libawt_xawt.so: libXtst.so.6: cannot open shared object file: No such file or directory at java.base/java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.base/java.lang.ClassLoader.loadLibrary0(Unknown Source) at java.base/java.lang.ClassLoader.loadLibrary(Unknown Source) at java.base/java.lang.Runtime.load0(Unknown Source) at java.base/java.lang.System.load(Unknown Source) at java.base/java.lang.ClassLoader$NativeLibrary.load(Native Method) at java.base/java.lang.ClassLoader.loadLibrary0(Unknown Source) at java.base/java.lang.ClassLoader.loadLibrary(Unknown Source) at java.base/java.lang.Runtime.loadLibrary0(Unknown Source) at java.base/java.lang.System.loadLibrary(Unknown Source) at java.desktop/java.awt.Toolkit$3.run(Unknown Source) at java.desktop/java.awt.Toolkit$3.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/java.awt.Toolkit.loadLibraries(Unknown Source) at java.desktop/java.awt.Toolkit.<clinit>(Unknown Source) at java.desktop/sun.awt.AppContext$2.run(Unknown Source) at java.desktop/sun.awt.AppContext$2.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/sun.awt.AppContext.initMainAppContext(Unknown Source) at java.desktop/sun.awt.AppContext.access$400(Unknown Source) at java.desktop/sun.awt.AppContext$3.run(Unknown Source) at java.desktop/sun.awt.AppContext$3.run(Unknown Source) at java.base/java.security.AccessController.doPrivileged(Native Method) at java.desktop/sun.awt.AppContext.getAppContext(Unknown Source) at java.desktop/javax.swing.SwingUtilities.appContextGet(Unknown Source) at java.desktop/javax.swing.UIManager.getLAFState(Unknown Source) at java.desktop/javax.swing.UIManager.maybeInitialize(Unknown Source) at java.desktop/javax.swing.UIManager.getDefaults(Unknown Source) at java.desktop/javax.swing.UIManager.put(Unknown Source) at ui.PlanAhead.<clinit>(SourceFile:169) ERROR: \[Common 17-70] Application Exception: JVM: Can't find class: ui/PlanAhead ERROR: \[Common 17-211] Error loading jvm. is there a way to fix that? Thanks
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asked a year ago

Error installing ATG drives

Hello, I'm trying to run Using-PCIM-Port example from https://github.com/awslabs/aws-fpga-app-notes/tree/master/Using-PCIM-Port Following the read me, I was able to Load AFI, (agfi-0d132ece5c8010bf7) build ATG drivers and by the time I install I hit on a Error sudo insmod atg_driver.ko slot=0x0f insmod: ERROR: could not insert module atg_driver.ko: Device or resource busy. dmesg logs: \[ 181.293259] IPv6: ADDRCONF(NETDEV_UP): ens3: link is not ready \[ 181.388658] IPv6: ADDRCONF(NETDEV_UP): ens3: link is not ready \[ 181.749638] IPv6: ADDRCONF(NETDEV_CHANGE): ens3: link becomes ready \[ 182.766973] tun: Universal TUN/TAP device driver, 1.6 \[ 182.771777] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> \[ 182.778610] virbr0: port 1(virbr0-nic) entered blocking state \[ 182.783989] virbr0: port 1(virbr0-nic) entered disabled state \[ 182.789778] device virbr0-nic entered promiscuous mode \[ 182.955985] virbr0: port 1(virbr0-nic) entered blocking state \[ 182.961290] virbr0: port 1(virbr0-nic) entered listening state \[ 182.966475] IPv6: ADDRCONF(NETDEV_UP): virbr0: link is not ready \[ 183.013277] virbr0: port 1(virbr0-nic) entered disabled state \[ 838.922911] Installing atg module \[ 838.926951] vendor: 1d0f, device: f001 \[ 838.931777] Enable result: 0 \[ 838.935241] xdma 0000:00:0f.0: BAR 0: can't reserve \[mem 0xc4000000-0xc5ffffff] \[ 838.943842] atg_driver: cannot obtain the OCL region How can I fix this ? I'm using a x16 card on centos. Edited by: TJ25 on Mar 30, 2020 9:02 AM
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asked 2 years ago

Question regarding f1.4 Instance

Hi Deep, I had launched up one F1.4x instance. the F1.4x has two fpga cards vs f1.2 which has just one. 1. If I just run one application, which fpga card will be used default? Or should I assign one FPGA to it --and how? 2. If I have multiple applications, then what fpga will be assigned to which fpga card, how can I do that? 3. Now I just already install ubuntu and vitis, and then build and installed the XRT (already install xrt.deb and aws-xrt.deb. Then by running xbutil scan, it reports one devic, which is not usable: ``` xbutil scan INFO: Found total 1 card(s), 0 are usable ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ System Configuration OS name: Linux Release: 4.15.0-1063-aws Version: #67-Ubuntu SMP Mon Mar 2 07:24:29 UTC 2020 Machine: x86_64 Model: HVM domU CPU cores: 16 Memory: 245842 MB Glibc: 2.27 Distribution: Ubuntu 18.04.4 LTS Now: Mon Mar 30 09:12:25 2020 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ XRT Information Version: 2.6.0 Git Hash: 0be8f75ca7e8a676ae5d385f453636c11567d584 Git Branch: master Build Date: 2020-03-30 08:22:33 XOCL: 2.6.0,0be8f75ca7e8a676ae5d385f453636c11567d584 XCLMGMT: unknown ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *[0] 0000:00:1d.0 xilinx_aws-vu9p-f1_dynamic_5_0(ID=0xabcd) user(inst=129) WARNING: card(s) marked by '*' are not ready, is MPD runing? run 'systemctl status mpd' to check MPD details. ``` Here is the mpd journal log (start from reboot, then I did a stop and restart mpd). ``` -- Reboot -- Mar 30 08:50:03 ip-172-31-19-142 systemd[1]: Started Xilinx Management Proxy Daemon (MPD). Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: started Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: aws: load default afi to 0000:00:1b.0 Mar 30 08:50:04 ip-172-31-19-142 mpd[1573]: found mpd plugin: /opt/xilinx/xrt/lib/libmpd_plugin.so Mar 30 09:18:05 ip-172-31-19-142 mpd[1573]: aws: load default afi to 0000:00:1d.0 Mar 30 09:19:10 ip-172-31-19-142 mpd[1573]: mpd caught signal 15 Mar 30 09:19:10 ip-172-31-19-142 systemd[1]: Stopping Xilinx Management Proxy Daemon (MPD)... Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: State 'stop-sigterm' timed out. Killing. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Killing process 1573 (mpd) with signal SIGKILL. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Main process exited, code=killed, status=9/KILL Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: mpd.service: Failed with result 'timeout'. Mar 30 09:20:40 ip-172-31-19-142 systemd[1]: Stopped Xilinx Management Proxy Daemon (MPD). Mar 30 09:20:56 ip-172-31-19-142 systemd[1]: Started Xilinx Management Proxy Daemon (MPD). Mar 30 09:20:56 ip-172-31-19-142 mpd[9324]: started Mar 30 09:20:56 ip-172-31-19-142 mpd[9324]: found mpd plugin: /opt/xilinx/xrt/lib/libmpd_plugin.so Mar 30 09:20:59 ip-172-31-19-142 mpd[9324]: aws: load default afi to 0000:00:1b.0 ``` BTW, I tried source vitis_runtime_setup.sh, it reports some error as below, does that matter?? Note I had built the XRT package and installed the xrt.deb then installed aws-xrt.deb. ``` WARNING: 4.15.0-1063-aws does not match one of recommended kernel versions 3.10.0-862.11.6.el7.x86_64 3.10.0-693.21.1.el7.x86_64 3.10.0-957.1.3.el7.x86_64 3.10.0-957.5.1.el7.x86_64 3.10.0-957.27.2.el7.x86_64 3.10.0-1062.4.1.el7.x86_64 3.10.0-1062.9.1.el7.x86_64WARNING: Xilinx Runtime not validated against your installed kernel version. INFO: Xilinx Vivado version is 2019.2 INFO: XRT installed. proceeding to check version compatibility INFO: Installed XRT version : 2019.2:0be8f75ca7e8a676ae5d385f453636c11567d584 ERROR: 2019.2:0be8f75ca7e8a676ae5d385f453636c11567d584 does not match recommended versions ``` Thanks a lot! Edited by: macleonsh on Mar 30, 2020 1:59 AM
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asked 2 years ago

DRC failing with multiple driver nets in cl_ocl_slv

Hi, I am adapting the _cl_dram_dma_ hdk example for my own project, and during the running of _aws_build_dcp_from_cl.sh_, I am encountering the DRC error below. I cannot find anywhere in the cl_ocl_slv module or instantiation that has the nets below, so I was hoping to get some insight into why the DRC is failing and how to go about fixing it. Thank you in advance. ``` Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xcvu9p' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcvu9p' Attempting to get a license: PartialReconfiguration Feature available: PartialReconfiguration Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads ERROR: [DRC MDRV-1] Multiple Driver Nets: Net WRAPPER_INST/CL/CL_OCL_SLV/I9[0] has multiple drivers: WRAPPER_INST/CL/CL_OCL_SLV/pipe[0][0]_i_2/O, and WRAPPER_INST/CL/CL_OCL_SLV/pipe[0][0]_i_1__3/O. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port I2C_FPGA_MEM_R_SCL expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port I2C_FPGA_QSFP28_R_SCL expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 1 Errors, 2 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. ```
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asked 3 years ago

Problem instanciating ILA in TCL workflow

Hello. I am trying to add an ILA to check the behavior of an AXI bus in my design. My design works in simulation but gets stuck on the FPGA. In order to debug this I want to check an AXI bus with an ILA. I used the following document as a reference : <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md> And the "hello_world" design as an example. I instanciated the debug bridge in my top with the following lines : ``` // Debug Bridge cl_debug_bridge CL_DEBUG_BRIDGE ( .clk(clk_main_a0), .S_BSCAN_drck(drck), .S_BSCAN_shift(shift), .S_BSCAN_tdi(tdi), .S_BSCAN_update(update), .S_BSCAN_sel(sel), .S_BSCAN_tdo(tdo), .S_BSCAN_tms(tms), .S_BSCAN_tck(tck), .S_BSCAN_runtest(runtest), .S_BSCAN_reset(reset), .S_BSCAN_capture(capture), .S_BSCAN_bscanid_en(bscanid_en) ); ``` I created an ILA using the IP catalog and a board diagram, the board diagram is because the ILA names the input ports probeXX instead of the AXI signal names and with the board diagram I can make a wrapper with the correct names. I added the ILA in the design and got the following errors on synthesis : ``` INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p' INFO: [Vivado_Tcl 4-550] User specified maximum number of URAM that can be cascaded is 2 CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_in.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_in.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_in.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_0_bs_core.vh' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog/xsdbm_v3_0_0_bs_core.vh) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/verilog/xsdbm_v3_0_0_bs_core.vh) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. CRITICAL WARNING: [filemgmt 20-1741] File 'xsdbm_v3_0_vl_rfs.v' is used by one or more modules, but with different contents, and may lead to unpredictable results: * bd_a493_xsdbm_0 (/home/user/design/aws-fpga/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/xsdbm_v3_0_vl_rfs.v) * test_axi_ila_1_ila_0_0 (/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v) Please reset and regenerate these modules to resolve the differences, or synthesize them independently. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17187 ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5838] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5867] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5900] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:5934] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9887] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9916] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9949] ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v:9983] Failed to read verilog '/home/user/design/aws-fpga/hdk/cl/developer_designs/new_synth/ip/bd/test_axi_ila_1/ipshared/6851/hdl/xsdbm_v3_0_vl_rfs.v' INFO: [Common 17-83] Releasing license: Synthesis 6 Infos, 17 Warnings, 4 Critical Warnings and 9 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details while executing "source -notrace ./synth_${CL_MODULE}.tcl" invoked from within "if {${cl.synth}} { source -notrace ./synth_${CL_MODULE}.tcl }" (file "create_dcp_from_cl.tcl" line 196) INFO: [Common 17-206] Exiting Vivado at Mon May 27 15:52:58 2019... ``` There is a conflict between the sources used by the debug bridge IP and my ILA IP. I followed the instructions in <https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md> Embedding Debug Cores in the CL. But I could not find how to solve this. Do you have any suggestion on how to solve this ? Thank you very much. Best Regads.
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asked 3 years ago

rtl_kernel examples in 2018.2: "requires 4 arguments" error (gen_xo.tcl)

Hello I recently updated my on-premise development tools to 2018.2, and the rtl_kernel examples are failing with error against the gen_XXX.tcl script. For example, for the following example: aws-fpga/SDAccel/examples/xilinx_2018.2/getting_started/rtl_kernel/rtl_vadd when I run this make command: make check TARGETS=hw_emu DEVICES=$AWS_PLATFORM_DYNAMIC_5_0 all I get the following error: ================================== mkdir -p xclbin /extra/opt/Xilinx/Vivado/2018.2.op2258646/bin/vivado -mode batch -source scripts/gen_xo.tcl -tclargs xclbin/vadd.hw_emu..xo vadd hw_emu ****** Vivado v2018.2.op (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source scripts/gen_xo.tcl # if { $::argc != 4 } { # puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n" # puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n" # exit # } ERROR: Program "scripts/gen_xo.tcl" requires 4 arguments! Usage: scripts/gen_xo.tcl <xoname> <krnl_name> <target> <device> INFO: \[Common 17-206] Exiting Vivado at Mon Apr 1 15:35:37 2019... mkdir -p xclbin /extra/opt/Xilinx/SDx/2018.2.op2258646/bin/xocc -l --xp "param:compiler.preserveHlsOutput=1" --xp "param:compiler.generateExtraRunData=true" -s -o xclbin/vadd.hw_emu..xclbin -t hw_emu --platform /home/tytra/aws-fpga/SDAccel/aws_platform/xilinx_aws-vu9p-f1-04261818_dynamic_5_0/xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xpfm xclbin/vadd.hw_emu..xo ****** xocc v2018.2_AR71715 (64-bit) **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ERROR: \[XOCC 60-602] Source file does not exist: /home/tytra/aws-fpga/SDAccel/examples/xilinx_2018.2/getting_started/rtl_kernel/rtl_vadd/xclbin/vadd.hw_emu..xo ERROR: \[XOCC 60-623] Unsupported input file type specified. make: *** \[xclbin/vadd.hw_emu..xclbin] Error 1 =================================== Can someone kindly advise on this? I get a similar error for any example in the rtl_kernel folder. Many thanks, Waqar.
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views
asked 3 years ago

Synthesis fails for axi_register_slice

My synthesis runs have been working fine until a recent set of innocuous modifications to the source. All of a sudden I'm getting errors in synthesis that have to do with an axi_register_slice I have in my cl_top.sv. I've triple checked the source is there and deleted the encrypted output. Has anyone else run into this problem? Does anyone have any ideas I can try? I'm unfortunately not able to share my source. The errors happen in RTL Elaboration and look like the following: INFO: \[Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189] Parameter C_FAMILY bound to: virtexuplus - type: string Parameter C_DATA_WIDTH bound to: 109 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axic_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:189] ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice_v2_1_15_axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v:2300] ERROR: \[Synth 8-6156] failed synthesizing module 'axi_register_slice' \[/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v:58] ERROR: \[Synth 8-5809] Error generated from encrypted envelope. \[/home/centos/cl_base/build/src_post_encryption/cl_top.sv:17] Thanks in advance, -Jack
4
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asked 3 years ago

SIGSEGV error during simulation.

While compiling my desing with the latest version of HDK Kit (HDK_VERSION=1.4.7) and Vivado version 2018.2, I get the following error. ERROR: \[XSIM 43-3316] Signal SIGSEGV received. I also found another user having the same error with an hdk example design itself as in thread below. I am attaching tail my elaborate.log below to provide another datapoint. https://forums.aws.amazon.com/thread.jspa?messageID=890695&#890695 ------------------------------------------------------------------------------------- WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:475] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:476] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:477] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:478] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:479] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:480] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:481] WARNING: \[VRFC 10-1635] non-void function initialize_memory_with_file called as a task without void casting \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:482] WARNING: \[VRFC 10-727] function device_bdr_ld has no return value assignment \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/fpga/fpga_ddr.svh:396] WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2527] WARNING: \[VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 \[/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv:2685] WARNING: \[VRFC 10-727] function match_char_after has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4562] WARNING: \[VRFC 10-727] function match_range has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:4575] WARNING: \[VRFC 10-727] function track_value_context has no return value assignment \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/http_parser.v:5545] WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1571] WARNING: \[VRFC 10-597] element index 7 into dq_temp is out of bounds \[../../../../../../../../aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv:1573] WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:182] WARNING: \[VRFC 10-597] element index 143 into sampled_val1_str is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/extract_content_type.v:195] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:117] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/ab_api_key_match.sv:118] WARNING: \[VRFC 10-1324] repetition multiplier must be positive \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/len_model_mgmt.sv:320] WARNING: \[VRFC 10-597] element index 16 into valid_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:147] WARNING: \[VRFC 10-597] element index 16 into sign_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:148] WARNING: \[VRFC 10-597] element index 16 into dividend_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:149] WARNING: \[VRFC 10-597] element index 16 into dividend_lo_bits_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:150] WARNING: \[VRFC 10-597] element index 16 into divisor_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:151] WARNING: \[VRFC 10-597] element index 16 into remainder_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:152] WARNING: \[VRFC 10-597] element index 16 into quotient_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:153] WARNING: \[VRFC 10-597] element index 16 into division_done_in is out of bounds \[/home/asanghi/project/valtix-hw/ade/design/rtl_json/divider.v:154] Completed static elaboration WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_cplx.sv" Line 855 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored. WARNING: \[XSIM 43-4127] File "/home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/cal/ddr4_v2_2_cal_top.sv" Line 1753 : The "System Verilog Assertion" is not supported yet for simulation. The statement will be ignored. INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2527, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv INFO: \[XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 2685, File /home/asanghi/project/aws_hdk/2018.2/aws-fpga/hdk/common/verif/models/sh_bfm/sh_bfm.sv ERROR: \[XSIM 43-3316] Signal SIGSEGV received. "elaborate.log" 159L, 29695C
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5
views
asked 3 years ago

Amazon Linux 2 and Xilinx Runtime Issue

Installation of the **Xilinx Runtime** on a clear **Amazon Linux 2** instance (which is RedHat based) leads to OpenCL runtime errors. **Xilinx Runtime (XRT) 2018.2_XDF.RC5** Installation instructions: https://github.com/aws/aws-fpga/blob/master/hdk/docs/SDxPatch_AR71715_and_XRT_installation_instructions.md#installing-xilinx-runtime-xrt-20182_xdfrc5 _Prerequisites_: Extra Packages for Enterprise Linux (EPEL) ``` sudo amazon-linux-extras install -y epel ``` ``` curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-xrt.rpm -o xrt_201802.2.1.0_7.5.1804-xrt.rpm curl -s https://s3.amazonaws.com/aws-fpga-developer-ami/1.5.0/Patches/XRT_2018_2_XDF_RC5/xrt_201802.2.1.0_7.5.1804-aws.rpm -o xrt_201802.2.1.0_7.5.1804-aws.rpm sudo yum install -y xrt_201802.2.1.0_7.5.1804-xrt.rpm sudo yum install -y xrt_201802.2.1.0_7.5.1804-aws.rpm ``` Example application: ``` #include <stdio.h> #include <CL/opencl.h> int main(){ cl_uint num_platforms; cl_int errcode_ret = clGetPlatformIDs(0, NULL, &num_platforms); if (errcode_ret != CL_SUCCESS){ fprintf(stderr, "Error: clGetPlatformIDs (%d)\n", errcode_ret); return EXIT_FAILURE; } printf("Info: %d opencl platform(s) found!", num_platforms); return EXIT_SUCCESS; } ``` Makefile: ``` SRCS = test.cpp OBJCTS = $(SRCS:.cpp=.o) EXE=test CC = g++ -Wall CFLAGS = -I${XILINX_XRT}/include LFLAGS = -L${XILINX_XRT}/lib -lxilinxopencl all: ${OBJCTS} ${CC} ${OBJCTS} ${LFLAGS} -o ${EXE} ${RM} ${OBJCTS} %.o: %.cpp ${CC} ${CFLAGS} -c ${<} -o ${@} clean: ${RM} ${OBJCTS} ${EXE} ``` 3 _sequential_ runs: $ ./test Segmentation fault $ ./test Segmentation fault $ ./test terminate called after throwing an instance of 'std::bad_alloc' what(): std::bad_alloc Aborted The problem must be related to boost library dependency! (Our JVM application stated **libboost.so** as the problematic frame.) **Note** that on a CentOS machine the same XRT installation works smoothly.
2
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0
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3
views
asked 3 years ago

Errors while running simulation

I am getting the following errors, while trying to simulate my design with AWS shell. It seems like the arch_package, proj_package declaration is missing. Where are they supposed to be declared. I already checked the the init.tcl file is being sourced and it contains the following lines: set AWSINSTALL "C:/AWS_Repo/aws-fpga" source $AWSINSTALL/hdk/common/shell_v04261818/hlx/hlx_setup.tcl Errors from the log: INFO: \[VRFC 10-2263] Analyzing SystemVerilog file "C:/AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_rdimm_wrapper/ddr4_db_delay_model.sv" into library xil_defaultlib INFO: \[VRFC 10-311] analyzing module ddr4_db_delay_model INFO: \[VRFC 10-2263] Analyzing SystemVerilog file "C:/AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/ddr4_model.sv" into library xil_defaultlib ERROR: \[VRFC 10-91] arch_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTable.sv:5] INFO: \[VRFC 10-311] analyzing module StateTable ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:1553] ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:1554] ERROR: \[VRFC 10-91] proj_package is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:2950] ERROR: \[VRFC 10-91] MAX_ROW_ADDR_BITS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:14] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:14] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:15] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:15] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:27] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:27] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:28] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:28] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:29] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:29] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:30] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:30] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:31] ERROR: \[VRFC 10-1775] range must be bounded by constant expressions \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:31] ERROR: \[VRFC 10-91] MAX_RANKS is not declared \[../../../../../../../../../../../../AWS_Repo/aws-fpga/hdk/common/verif/models/ddr4_model/StateTableCore.sv:32] INFO: \[#UNDEF] Sorry, too many errors..
1
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0
votes
1
views
asked 3 years ago
  • 1
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