Questions tagged with FPGA Development

I cannot pop up GUI when I use mobaxterm if I set emulation debug=gui in Amazon AMI here https://aws.amazon.com/marketplace/pp/prodview-hxbanceez6tso. It should pop up if I set it when I do HW...

Hi,  Look at the above image. From **module A**, a gated clock is going to **module B**. We found that **module...

Hi, I was trying to read a memory from FPGA using DMA read and I got the following output. a4, e, 25, 3c, 28, 85, dc, 5, **a4, e, 25, 3c, 28, 85, dc, 5**. 8 bytes are repeated here. The expected...

Hi, I want to write two different registers/memory parallelly using DMA. I tried using multithreading concept. But writing is not happening as expected. I mean there is a time delay. How to avoid it?...

Hi, I want to store 500 MB of data in DDR and it should be feed to my design as 64 bit data continuously using 40 MHz clock (Note: 40 MHz clock is generated using MMCM). How to achieve this.? Thank...

Hi, we are seeing performance drop when we access specific address pattern from DDR. Please find the below details. in a single test we read same address repeatedly as mentioned below rd_addr is...

Hi there, Is there a way that CL can control the XDMA inside the Shell in the AWS F1? I have a usecase where CL needs to setup a DMA transfer from internal memory to Host. A separate question, Is...

I encountered an error during the official tutorial. (https://github.com/aws/aws-fpga/blob/master/Vitis/README.md) I followed the tutorial in AWS F1(f1.2xlarge) instance / oregon FPGA Developer AMI...

I needed a phase-shifted (relative to the clk_main_a0) clock for my CL, and I implemented that using an MMCME4_ADV in my design. I ran into the well-known sub-optimal placement issues. When I did this...

Hi, I have to connect my design with ARM processor and I have to create 2 AFIs with the same design. One is transmitter and another is receiver. But both have to be configured in a different way so...

Hi, Getting the following error while implementing my custom logic. ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net...

I am trying to do some optimization for network traffic handling by utilizing FGPA acceleration on AWS [F1?]. Per my understanding the F1 service is based on Xilinx Alveo SmartNIC hardware. So my...