All Content tagged with FPGA Development

Hi all.. I've tried to create aws-fpga-images with xclbin files generated by v++. the detailed situation I've met now is below, 1) created "awsxclbin files" using command "**aws ec2 create-fpga-...

I noticed the latest developer AMI has 2022.1 installed, and would like to upgrade my fork of aws-fpga to use it (to workaround a Vivado bug). When will there be a cut of aws-fpga supporting that vers...

Hello, I have a problem with the installation, what should I do and is this normal?? 

Hello, I developed an FPGA accelerator for f1-instances. Several years ago I made it. I set it as public. Now, I want to use it again, but cannot load it. Here are some details. In short, it is my i...

I’m aware of the supported devices for FreeRTOS [here](https://freertos.org/RTOS_ports.html?_ga=2.165111679.1380880367.1658266296-1765742849.1658253566), but I’m wondering if all of these also fully s...

Hi, I'm new to AWS FPGA development. I notice that AWS F1.4xlarge (and F1.16xlarge) instances support effective P2P communication between FPGAs, without the help of the host. But the example from Xil...

I have a wide and deep shift register in my design that I want to control using a gated clock. Its size and distribution throughout the entire device make a clock enable an inferior option from a rout...

Hi, I'm an F1 AWS user, and I'm trying to run the PCIE Write Combine example on a cl_dram_dma example design: https://github.com/awslabs/aws-fpga-app-notes/tree/master/Using-PCIe-Write-Combining In...

How can I select a specific version of FPGA Developer AMI? AWS Console offers only version Ver 1.11.4 for selection. I work with third party tool which is build on top of Vivado and it works fine with...

Hello, I am currently using Vitis hls2021.2 to compile an FPGA program. The instance I use is t2.2x. My problem is that there is no error during the compilation process, But my compilation log shows t...

# Problem: I started an EC2 instance running the FPGA Developer AMI, and tried to use Vivado to create a new project that wraps custom Verilog Designs for use in Amazon F1 FPGAs. So far, I cannot get...

# Steps: 1. git clone https://github.com/aws/aws-fpga.git 2. source hdk_setup from the aws_fpga directory 3. create Vivado_init.tcl with line: source $::env(HDK_SHELL_DIR)/hlx/hlx_setup.tcl 4. vivado...