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All Content tagged with FPGA Development
Accelerate your applications with FPGA technology
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MY VPS DOES NOT WORK, WHEN I OPEN IT IT TAKES 2 MINUTES TO JUST OPEN AND WHEN I DOES I GET A BLACK SCREEN AND AFTER A FEW SECONDS IT JUST TURNS OFF AND RETURNS ME TO MY DESKTOP.
TO SUM IT ALL UP YOUR ...
Is there any utility in the aws-fpga github repository that helps transfering data to host DDR memory?
I would like to use a DMA in the FPGA to transfer data directly to the host using the "S_AXI_PCIM...
Hi,
I am new to AWS EC2 F1 FPGAs. I am trying to build cl_helloworld.sv example. When I am compiling synthesis failing due to following error.
ERROR: [Synth 8-5809] Error generated from encrypted env...
Hi everyone,
While doing synthesis for creating AFI using vivado IPI , I get this error.
**ERROR: [Common 17-107] Cannot change read-only property 'is_locked'.**
Resolution: Please refer to Vivado ...
hi, I am new at AWS and at f1 instance. I connected to f1 instance and to remote desktop but I cant understand how to go further from that point. What I want to ask is
1) Do you know any good tutorial...
Hello.
I have a few of questions during checking STA for implementing FPGA design for F1 instance.
During STA, there are some violation points that I cannot understand. I uploaded a image to give y...
Hello,
Is there a way to create your own clock recipe instead of whats provided in https://github.com/aws/aws-fpga/blob/master/hdk/docs/clock_recipes.csv
Say for example I want to create a 160 MHz c...
Hi,
I am using the AWS F1 instance to create my own accelerator in CL portion. There are multiple blocks in my hierarchy and what I want to be able to do is assign a hierarchical block to my own pblo...
Hello aws, depites of the aws support of https://repost.aws/questions/QUn-Z39lZhRaS_g93s0U32Eg/how-should-i-delete-afi-that-is-stuck-in-pending,
AFI gen of my design with full functionality still has...
I'd like to share FPGA images with just accounts in my company's AWS organization.
https://awscli.amazonaws.com/v2/documentation/api/latest/reference/ec2/modify-fpga-image-attribute.html suggests app...
I'd created several AFIs that are all stuck in 'pending' from the end of Aug.
the relative thread is https://repost.aws/questions/QU-CsdCyAqTxedKYkG9PuwtA/pending-create-fpga-images-using-aws-ec-2
wh...
So I am using the AWS F1 instance with a modified CL_SDE example from the GIT repo. We modified the HDL in the example to allow us to invert the loopbacked data through a control register, stop the i...