Questions tagged with FPGA Development
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Hello, I am having an issue with a program running on an Amazon F1 FPGA instance.
When I run the program, the program gives me this error message when I run it with the environment variable...
0
answers
0
votes
190
views
asked 14 days agolg...
Right now I'm working to put a MicroBlaze core with Vivado IP Integrator flow, however, I can't connect to the MicroBlaze Debug Module (MDM) when I deployed in on an EC2 F1 instance.
My design is as...
1
answers
0
votes
42
views
asked a month agolg...
Can I use "host memory access" in Amazon F1 instance? Alveo supports such a feature that provides DMA bypass capability used for FPGA to transfer date to the host on a No-DMA platform. Since I have...
Accepted AnswerFPGA Development
1
answers
0
votes
83
views
asked 2 months agolg...
Hi,
Is it possible to upgrade the F1 nodes' Viti's version to 2023.2?
I am currently using the AMI 1.2 image.
1
answers
0
votes
135
views
asked 3 months agolg...
To check AMI and AFI approved by others using AWS cli,
I used the command "aws ec2 description-fpga-images > output",
An error occurred (UnauthorizedOperation) when calling the DescribeFpgaImages...
1
answers
0
votes
232
views
asked 4 months agolg...
hello,
on the F1 instances, is there a way to access the full 72 bit of the DDR4 banks from the CL?
our application would benefit from giving up ECC support, and having access to the extra bits in...
1
answers
0
votes
174
views
asked 5 months agolg...
I am following the documentation linked below. I was able to build the image successfully but when I try to complete step 7 I get an error in the console also shown below. Since the script that runs...
0
answers
0
votes
146
views
asked 6 months agolg...
I cannot pop up GUI when I use mobaxterm if I set emulation debug=gui in Amazon AMI here https://aws.amazon.com/marketplace/pp/prodview-hxbanceez6tso.
It should pop up if I set it when I do HW...
1
answers
0
votes
225
views
asked 7 months agolg...
Hi,
![Enter image description here](/media/postImages/original/IMHuUteqzyRb6Kfpz-x8mzJw)
Look at the above image. From **module A**, a gated clock is going to **module B**. We found that **module...
1
answers
0
votes
222
views
asked 7 months agolg...
Hi,
I was trying to read a memory from FPGA using DMA read and I got the following output.
a4,
e,
25,
3c,
28,
85,
dc,
5,
**a4,
e,
25,
3c,
28,
85,
dc,
5**.
8 bytes are repeated here.
The expected...
Accepted AnswerFPGA Development
4
answers
0
votes
276
views
asked 8 months agolg...
DMA restrictionslg...
Hi,
I want to write two different registers/memory parallelly using DMA. I tried using multithreading concept. But writing is not happening as expected. I mean there is a time delay. How to avoid it?...
1
answers
0
votes
210
views
asked 8 months agolg...
Hi,
I want to store 500 MB of data in DDR and it should be feed to my design as 64 bit data continuously using 40 MHz clock (Note: 40 MHz clock is generated using MMCM). How to achieve this.?
Thank...
Accepted AnswerFPGA Development
1
answers
0
votes
206
views
asked 8 months agolg...