Questions tagged with FPGA Development
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Starting December 21 2021, AWS Forums was made Read Only. While the AWS Forums banners are requesting customers to post on AWS Re:Post, we strongly recommend posting on the aws-fpga Github Issues...
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asked 2 years agolg...
Beginning December 31, 2021 AWS will disable new AFI creations of designs made using Xilinx 2017.4 toolsets. We will also sunset FPGA Developer AMI v1.4.0 and calls to EC2 CreateFpgaImage:...
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167
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asked 2 years agolg...
DDR data retentionlg...
Looking into getting data retention working for my design and I came across below requirement in the documentation.
"The AFI must use all four DDR controllers. (All of DDR_A_PRESENT,...
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349
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asked 3 years agolg...
Tried to spin up an F1 instance in the NoVA data center yesterday and was unable to for at least 15 minutes after which I gave up. Haven't had this happen before and was curious as to the reason and...
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299
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asked 3 years agolg...
cl_debug_bridgelg...
I am trying to use the cl_ila same as in cl_dram_dma., i.e, I have the 2 AXI busses to monitor using ILA.
However the synthesis script cannot seem to find the cl_debug_bridge module.
Which...
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200
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asked 3 years agolg...
Hey everyone,
I've recently bumped to a newer AMI which brings in Vivado 2020.2, I was previously on 2018.4. I've noticed that Vivado has gotten much more strict about hiding the names of cells...
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203
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asked 3 years agolg...
Locally done by instantiating an MMCM and then accessing its PSEN, PSINCDEC, PSCLK and PSDONE ports.
I'm just getting started but couldn't find a concrete answer to this, sorry if it's a dumb...
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190
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asked 3 years agolg...
Hi. I am using FPGA Developer AMI 1.11.0 and was running hello_world example from https://github.com/aws/aws-fpga/blob/master/Vitis/README.md, using "make all TARGET=hw DEVICE=$AWS_PLATFORM"
I am...
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328
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asked 3 years agolg...
Hi All,
Based on the output of lsmod command and documents (https://github.com/aws/aws-fpga/blob/master/sdk/linux_kernel_drivers/xdma/xdma_install.md ), the default driver for CentOS is xocl.
But...
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331
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asked 3 years agolg...
Seeing a intra-clock timing violation between clocks "rdck" and "tck" (both associated by dbg_hub) after enabling DDRA and connecting a CDMA IP to it.
Notes:
1) dbg_hub is automatically...
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243
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asked 3 years agolg...
Hi,
I referred to Multiple devices example project and updated my project to work with multiple fpga devices <https://github.com/Xilinx/Vitis_Accel_Examples/tree/2020.2/sys_opt/multiple_devices>. I...
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269
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asked 3 years agolg...
Future of FPGA AMIlg...
Hello all,
I'm interested to hear if AWS is willing to share their plans on future version of OS that will be used for FPGA AMI. Currently, FPGA AMI is running on CentOS 7 (or Amazon Linux 2,...
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389
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asked 3 years agolg...