Questions tagged with FPGA Development
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I am using aws_build_dcp_from_cl.sh script to run synthesis and once synthesis is complete tar file is generated from which I can generate afi. When I run synthesis in vivado gui I can see...
1
answers
0
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192
views
asked 3 years agolg...
We have two xpfm setup (basically two different versions of the F1 shell) and we have generated bitfiles with them. The name of these two xpfm files are:
*...
2
answers
0
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229
views
asked 3 years agolg...
Hi there,
Once I try to load my local image, I obtain the following error:
$ sudo fpga-load-local-image -S 0 -I agfi-0c5a45f4871941614
Error: (12) cl-id-mismatch
The vendor and device ID...
2
answers
0
votes
242
views
asked 3 years agolg...
Hi there,
Once I try to load my local image, I obtain the following error:
$ sudo fpga-load-local-image -S 0 -I agfi-0c5a45f4871941614
Error: (12) cl-id-mismatch
The vendor and device ID...
1
answers
0
votes
204
views
asked 3 years agolg...
Bridge to AXI 4lg...
Hi,
Is there ant common solution for a bridge from APB in Xilinx IP lib ( or other simple parallels bus) to AXI 4?
I am asking it because I need to implement bridge from the APB bus to the DDR...
3
answers
0
votes
303
views
asked 3 years agolg...
I’m using AMI/1.8.1 and vitis/2019.2. And I’m using myself dut. Now I’m using aurora_64b66b. I want to use k code(K28.5). Where to view the K code(K28.5) for Aurora64B66B?
1
answers
0
votes
180
views
asked 3 years agolg...
vivado crushlg...
Hey,
I'm connecting to my F1 instance using SSH when trying to start vivado I get:
***** Vivado v2020.1 (64-bit)
**** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
**** IP Build...
5
answers
0
votes
504
views
asked 3 years agolg...
Hello! I'm trying to run a few examples with the Vitis sparse library (https://github.com/Xilinx/Vitis_Libraries/tree/master/sparse). Specifically, I'm trying to run the matrix vector multiplication...
1
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0
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200
views
asked 3 years agolg...
Hello,
The build strategy used in the flow should be mentioned in the manifest sent to AFI generation. currently there are 5 strategies (DEFAULT/BASIC/EXPLORE/TIMING/CONGESTION).
Is the...
2
answers
0
votes
194
views
asked 4 years agolg...
Hi
I am trying to build the DMA-based HDK example (cl_dram_dma) on the FPGA Developer AMI on an EC2 instance. After several hours I hit the following (as recorded in my nohup.out file):
...
3
answers
0
votes
263
views
asked 4 years agolg...
Hi There
I am looking for the next level of detail on how the XDMA registers are mapped into BAR2 of the AppPF in the AWS F1 shell. I know I **could** read the XDMA driver code and try and work...
2
answers
0
votes
311
views
asked 4 years agolg...
Looks like in the dram_dma exmple there are a number of floor planning directives to improve timing/routability.
I currently do not use DRAM or the DMA in my cl, should I include these constraints...
1
answers
0
votes
181
views
asked 4 years agolg...