System verilog generate warnings in DDR controller of AWS FPGA shell

Question

Hi,

I see the following system verilog warnings from the DDR controller when running a test on my design. I am including the directory and command below:

directory=aws-fpga/hdk/cl/developer_designs/cl_xxx/verif/scripts
command=make TEST=

Here are the warnings. Has anyone seen these before and do they prevent you from running an FPGA AMI image on an F1 instance later?

WARNING: [VRFC 10-2821] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/controller/ddr4_v2_2_mc_ecc_fi_xor.sv:125]WARNING: [VRFC 10-2821] generate block is allowed only inside loop and conditional generate in SystemVerilog mode [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/ddr4_core/rtl/controller/ddr4_v2_2_mc_ecc_fi_xor.sv:125]

Thanks!
Kelvin

Accepted Answer

Hello,

Looking into the details, the warning message indicates that a generate block is being used outside of a loop or conditional generate statement in the System Verilog code. To troubleshoot this warning you can either move the generate block inside a loop or a conditional generate statement or remove the generate block if it is not necessary.

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To troubleshoot the warning, could you please try the following steps:

- Check the line number mentioned in the warning message to locate the generate block in the code.
- Determine whether the generate block is required for the functionality of the code. If not, you can remove it.
- If the generate block is necessary, identify the loop or conditional generate statement where it can be placed.
- Move the generate block inside the loop or conditional generate statement.
- Save the changes to the code and recompile to verify that the warning message has been resolved.

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Let me know if you have any further queries. Thank you for your interest in re:Post community.

Best Regards, Ashish

System verilog generate warnings in DDR controller of AWS FPGA shell

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