F1 FPGA LUT utilization target

My design is consumes ~55% LUTs. The RAM and DSP utilization is pretty low < 10%. When I try add more logic it runs into congestion issues. So, I am trying to reduce some bus widths. However, I would like to know if there is a good rule of thumb on what LUT utilization can be target without hitting congestion issues. I am hoping you guys have such data from various customer datapoints. Thanks