ddr_is_ready not being asserted

Question

Hi,  
    I am simulating my design after connecting it to the DDRB, but ddrb_is_ready doesnt get asserted.   
  
I am using the IPI flow. I have customized the F1 IP to enable DDRB interface and connected the DDRB AXI interface and the ddrb_is_ready signal to my design. Now when I run the test, ddrb_is_ready is not asserted. I have ran the simulation for more than 280us, but don't see the ddrb_is_ready going up. Below is the instruction sequence from my test.sv. What am I missing.  
  
  initial begin  
      tb.power_up();  
      tb.nsec_delay(5000);  
  
      //Read the status register (original wait for 400ns then enable, #40000)  
      tb.peek_bar1(0, `IP_STATUS_REG, rdata, 6'h0);  
  
      // allow memory to initialize  
      tb.nsec_delay(270000);  
      $finish;  
    end

Answer

Hello fpgamagic,  
I guess you have missed the poke_stat routine. That releases the reset to the DDR B.  
     // tb.poke_stat(.addr(8'h0c), .ddr_idx(0), .data(32'h0000_0000));  
      tb.poke_stat(.addr(8'h0c), .ddr_idx(1), .data(32'h0000_0000));  
      //tb.poke_stat(.addr(8'h0c), .ddr_idx(2), .data(32'h0000_0000));  
  
Add this before the peek_bar routine and you should see that ddrb_is_ready is asserted after the delay.  
  
Regards  
Bala

Answer

@awsbalasram Thanks. I found and ended up adding tb.init_ddr() to my routine. Which basically includes exactly the statements pointed out by you. After this I can confirm that the ddr_is_ready signal goes up.  
Thanks  
fpgamagic

ddr_is_ready not being asserted

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